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STK14C88-M PDF даташит

Спецификация STK14C88-M изготовлена ​​​​«Simtek» и имеет функцию, называемую «32K x 8 AUTOSTORE nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM».

Детали детали

Номер произв STK14C88-M
Описание 32K x 8 AUTOSTORE nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM
Производители Simtek
логотип Simtek логотип 

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STK14C88-M Даташит, Описание, Даташиты
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STK14C88-M
32K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
MIL-STD-883
FEATURES
• Nonvolatile Storage without Battery Problems
• 35ns and 45ns Access Times
• “Hands-off” Automatic STORE with External
68µF Capacitor on Power Down
STORE to EEPROM Initiated by Hardware,
Software or AutoStore™ on Power Down
RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 100,000 STORE Cycles to EEPROM
• 10-Year Data Retention in EEPROM
• Single 5V + 10% Operation
• Not Sensitive to Power On/Off Ramp Rates
• No Data Loss from Undershoot
• 32-Pad LCC and 32-Pin 300 mil CDIP Packages
DESCRIPTION
The Simtek STK14C88-M is a fast static RAM with a
nonvolatile, electrically erasable PROM element
incorporated in each static memory cell. The SRAM
can be read and written an unlimited number of
times, while independent nonvolatile data resides in
EEPROM. Data transfers from the SRAM to the
EEPROM (the STORE operation) can take place auto-
matically on power down. A 68µF or larger capacitor
tied from VCAP to ground guarantees the STORE
operation, regardless of power-down slew rate or
loss of power from “hot swapping”. Transfers from
the EEPROM to the SRAM (the RECALL operation)
take place automatically on restoration of power. Ini-
tiation of STORE and RECALL cycles can also be
software controlled by entering specific read
sequences. A hardware STORE may be initiated with
the HSB pin.
BLOCK DIAGRAM
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
EEPROM ARRAY
512 x 512
STATIC RAM
ARRAY
512 x 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCCX VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
PIN CONFIGURATIONS
HSB
VCAP
A 14
A 12
A7
A6
A5
A4
A3
NC
A2
A1
A0
DQ 0
DQ 1
DQ 2
V SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCCX
31 HSB
30 W
29 A13
A
4
5
3
2
1
32 31 30
29
A
28 A8
6
A6
13
28 A
27 A9
5
A7
8
27 A
26 A11
25 G
4
A8
3
9
32 26 A
11
NC 9
25 G
24 NC
A 10
LCC
24 NC
23 A10
2
A 11
23 A
22 E
1
10
A 12
22 E
21
DQ 7
0
DQ
13
21 DQ
20 DQ 6
0 14 15 16 17 18 19 20
7
19 DQ 5
18 DQ 4
17 DQ 3
A0 - A13
G
E
W
PIN NAMES
A0 - A14
DQ0 -DQ7
E
W
G
HSB
VCCX
VCAP
VSS
Address Inputs
Data In/Out
Chip Enable
Write Enable
Output Enable
Hardware Store Busy (I/O)
Power (+ 5V)
Capacitor
Ground
April 1999
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STK14C88-M Даташит, Описание, Даташиты
STK14C88-M
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (VCC + 0.5V)
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (VCC + 0.5V)
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
DC CHARACTERISTICS
Note a:
Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
(VCC = 5.0V ± 10%)e
SYMBOL
ICC1b
ICC2c
ICC3b
ICC4c
ISB1d
ISB2d
IILK
IOLK
VIH
VIL
VOH
VOL
VBL
TA
PARAMETER
Average VCC Current
Average VCC Current during STORE
Average VCC Current at tAVAV = 200ns
Average VCAP Current during AutoStore
Cycle
Average VCC Current
(Standby, Cycling TTL Input Levels)
VCC Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
MILITARY
MIN MAX
90
85
6
15
4
30
28
3
±1
2.2
VSS – .5
2.4
– 55
±5
VCC + .5
0.8
0.4
0.4
125
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
V
°C
NOTES
tAVAV = 35ns
tAVAV = 45ns
All Inputs Don’t Care, VCC = max
W (VCC – 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
tAVAV = 35ns, E VIH
tAVAV = 45ns, E VIH
E (VCC – 0.2V)
All Others VIN 0.2V or (VCC – 0.2V)
VCC = max
VIN = VSS to VCC
VCC = max
VIN = VSS to VCC, E or G VIH
All Inputs
All Inputs
IOUT = – 4mA except HSB
IOUT = 8mA except HSB
IOUT = 3mA
Note b:
Note c:
Note d:
Note e:
ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
IECC2VaInHdwIiCllCn4oat rperothdeucaevesrtaagnedbcyurcruernrtesnrteleqvueirlesdufnotril
the duration of the respective STORE
any nonvolatile cycle in progress has
cycles
timed
(tSTORE
out.
)
.
VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is con-
nected to ground.
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
CAPACITANCEf (TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX UNITS CONDITIONS
CIN
COUT
Input Capacitance
Output Capacitance
5
7
pF V = 0 to 3V
pF V = 0 to 3V
Note f: These parameters are guaranteed but not tested.
OUTPUT
255 Ohms
30 pF
INCLUDING
SCOPE
AND FIXTURE
Figure 1: AC Output Loading
April 1999
5-44









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STK14C88-M Даташит, Описание, Даташиты
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
1 tELQV
2 tAVAVg
3 tAVQVh
4 tGLQV
5 tAXQXh
6 tELQX
7 tEHQZ
8 tGLQX
9 tGHQZi
10 tELICCH
11 tEHICCL
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
SRAM READ CYCLE #2: E Controlledg
ADDRESS
2
tAVAV
1
tELQV
E
6
tELQX
G
DQ (DATA OUT)
ICC
8
tGLQX
4
tGLQV
10
tELICCH
STANDBY
ACTIVE
STK14C88-M
(VCC = 5.0V ± 10%)e
STK14C88-35M
MIN MAX
STK14C88-45M
MIN MAX
UNITS
35 45 ns
35 45 ns
35 45 ns
15 20 ns
3 3 ns
5 5 ns
13 15 ns
0 0 ns
13 15 ns
0 0 ns
35 45 ns
DATA VALID
11
tEHICCL
7
tEHQZ
9
tGHQZ
DATA VALID
April 1999
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