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STK11C88 PDF даташит

Спецификация STK11C88 изготовлена ​​​​«Simtek» и имеет функцию, называемую «32Kx8 SoftStore nvSRAM».

Детали детали

Номер произв STK11C88
Описание 32Kx8 SoftStore nvSRAM
Производители Simtek
логотип Simtek логотип 

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STK11C88 Даташит, Описание, Даташиты
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FEATURES
• 25, 45 ns Read Access & R/W Cycle Time
• Unlimited Read/Write Endurance
• Pin Compatible with Industry Standard SRAMs
• Software-initiated STORE and RECALL
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 1 Million Store Cycles
• 100-Year Non-volatile Data Retention
• Single 5V ± 10% Power Supply
• Commercial and Industrial Temperatures
• 28-pin 300-mil and 330-mil SOIC Packages
(RoHS-Compliant)
DESCRIPTION
STK11C88
32Kx8 SoftStore nvSRAM
The Simtek STK11C88 is a 256Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
Data transfers under software control to the non-vol-
atile storage cell (the STORE operation). On power
up, data is automatically restored to the SRAM (the
RECALL operation). RECALL operations are also
available under software control.
The Simtek nvSRAM is the first monolithic non-
volatile memory to offer unlimited writes and reads.
It is the highest performance, most reliable non-
volatile memory available.
BLOCK DIAGRAM
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
QUANTUM TRAP
512 x 512
STATIC RAM
ARRAY
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
A13 – A0
G
E
W
Document Control #ML0012 Rev 0.3
February 2007









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STK11C88 Даташит, Описание, Даташиты
STK11C88
PIN CONFIGURATIONS
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 11
DQ1 12
DQ2 13
VSS 14
28 VCC
27 W
26 A13
25 A8
24 A9
23 A11
22 G
21 A10
20 E
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
28 - Pin 300 mil SOIC
28 - Pin 330 mil SOIC
PIN DESCRIPTIONS
Pin Name
A14-A0
DQ7-DQ0
E
W
G
VCC
VSS
Input
I/O
Input
Input
I/O
Input
Power Supply
Power Supply
Description
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power: 5.0V, ±10%
Ground
Document Control #ML0012 Rev 0.3
February 2007
2









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STK11C88 Даташит, Описание, Даташиты
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
STK11C88
Note a:
Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
(VCC = 5.0V ± 10%)
SYMBOL
ICC1b
ICC2c
ICC3b
ISB1d
ISB2d
IILK
PARAMETER
Average VCC Current
Average VCC Current during STORE
Average VCC Current at tAVAV = 200ns
5V, 25°C, Typical
Average VCC Current
(Standby, Cycling TTL Input Levels)
VCC Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
IOLK Off-State Output Leakage Current
VIH Input Logic “1” Voltage
VIL Input Logic “0” Voltage
VOH Output Logic “1” Voltage
VOL Output Logic “0” Voltage
TA Operating Temperature
COMMERCIAL
MIN MAX
97
70
3
10
30
22
750
INDUSTRIAL
MIN MAX
100
70
3
UNITS
mA
mA
mA
10 mA
31 mA
23 mA
750 μA
±1 ±1 μA
±5 ±5 μA
2.2
VSS – .5
2.4
VCC + .5 2.2 VCC + .5
0.8 VSS – .5 0.8
2.4
0.4 0.4
0 70 –40 85
V
V
V
V
°C
NOTES
tAVAV = 25ns
tAVAV = 45ns
All Inputs Don’t Care, VCC = max
W (V CC– 0.2V)
All Others Cycling, CMOS Levels
tAVAV = 25ns, E VIH
tAVAV = 45ns, E VIH
E (V CC - 0.2V)
All Others VIN 0.2V or (VCC – 0.2V)
VCC = max
VIN = VSS to VCC
VCC = max
VIN = VSS to VCC, E or G VIH
All Inputs
All Inputs
IOUT = – 4mA
IOUT = 8mA
Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE ) .
Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCEe (TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX UNITS CONDITIONS
CIN
COUT
Input Capacitance
Output Capacitance
5
7
pF ΔV = 0 to 3V
pF ΔV = 0 to 3V
Note e: These parameters are guaranteed but not tested.
OUTPUT
255 Ohms
5.0V
480 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
Document Control #ML0012 Rev 0.3
February 2007
3










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