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PDF AZ10LVEL32 Data sheet ( Hoja de datos )
| Número de pieza | AZ10LVEL32 | |
| Descripción | ECL/PECL / 2 Divider | |
| Fabricantes | Arizona Microtek | |
| Logotipo |  |
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AZ10LVEL32
AZ100LVEL32
ARIZONA MICROTEK, INC.
ECL/PECL ÷ 2 Divider
FEATURES
• Operating Range of 3.0V to 5.5V
• 470ps Propagation Delay
• 3.0GHz Toggle Frequency
• High Bandwidth Output Transitions
• Direct Replacement for ON
Semiconductor MC10EL/LVEL32 &
MC100EL/LVEL32
PACKAGE AVAILABILITY
PACKAGE
PART NUMBER MARKING NOTES
SOIC 8 Green /
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL32DG
AZM100G
LVEL32
1,2
TSSOP 8 Green /
RoHS Compliant /
Lead (Pb) Free
AZ100LVEL32TG
AZHG
LV32
1,2
MLP 8 (2x2) Green
/ RoHS Compliant /
Lead (Pb) Free
AZ100LVEL32NG
C2G
<Date Code>
1,3
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
2 Date code format: “Y” or “YY” for year followed by “WW” for week on
underside of part.
3 Date code format: “Y” for year followed by “WW” for week.
DESCRIPTION
The AZ10/100LVEL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising
edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization
of multiple LVEL32’s in a system.
The LVEL32 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device.
For single-ended input applications, the VBB reference should be connected to one side of the CLK/C¯¯L¯K¯ differential
input pair. The input signal is then fed to the other CLK/¯C¯L¯K¯ input. The VBB pin should be used only as a bias for
the LVEL32 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a
0.01μF capacitor.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
PIN DESCRIPTION
PIN
CLK, C¯L¯¯K
RESET
VBB
Q, Q¯
VCC
VEE
FUNCTION
Clock Inputs
Asynchronous Reset
Reference Voltage Output
Data Outputs
Positive Supply
Negative Supply
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
RESET 1
CLK 2
CLK 3
8 VCC
R
7Q
÷2
6Q
VBB 4
5 VEE
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
1 page  
AZ10LVEL32
AZ100LVEL32
PACKAGE DIAGRAM
SOIC 8
NOTES:
1. DIMENSIONS D AND E DO NOT
INCLUDE MOLD PROTRUSION.
2. MAXIMUM MOLD PROTRUSION
FOR D IS 0.15mm.
3. MAXIMUM MOLD PROTRUSION
FOR E IS 0.25mm.
DIM
A
A1
A2
A3
bp
c
D
E
e
HE
L
Lp
Q
v
w
y
Z
θ
MILLIMETERS
MIN
MAX
1.75
0.10 0.25
1.25 1.45
0.25
0.36 0.49
0.19 0.25
4.8 5.0
3.8 4.0
1.27
5.80 6.20
1.05
0.40 1.00
0.60 0.70
0.25
0.25
0.10
0.30 0.70
0O 8O
INCHES
MIN
MAX
0.069
0.004 0.010
0.049 0.057
0.01
0.014 0.019
0.0075 0.0100
0.19 0.20
0.15 0.16
0.050
0.228 0.244
0.041
0.016 0.039
0.024 0.028
0.01
0.01
0.004
0.012
0O
0.028
8O
July 2006 * REV - 0
www.azmicrotek.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AZ10LVEL32.PDF ] | |
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