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PDF XRT72L53 Data sheet ( Hoja de datos )
| Número de pieza | XRT72L53 | |
| Descripción | THREE CHANNEL DS3/E3 FRAMER IC | |
| Fabricantes | Exar Corporation | |
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PRELIMINARY
XRT72L53
MAY 2001
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.8
GENERAL DESCRIPTION
The XRT72L53, 3 Channel DS3/E3 Framer IC is de-
signed to accept User Data from the Terminal Equip-
ment and insert this data into the Payload bit-fields
within an Outbound DS3/E3 Data Stream. Further,
the Framer IC is also designed to receive an Inbound
DS3/E3 Data Stream (from the Remote Terminal
Equipment) and extract out the User Data.
The XRT72L53 DS3/E3 Framer device is designed to
support full-duplex data flow between Terminal Equip-
ment and an LIU (Line Interface Unit) IC. The Framer
Device will transmit, receive and process data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and E3-
ITU-T G.832 (November 1995 and October 1998 Re-
visions) Framing Formats.
The XRT72L53 DS3/E3 Framer IC consists of three
Transmit sections, three Receiver sections, three Per-
formance Monitor Sections and a Microprocessor in-
terface.
The Transmit Sections, include a Transmit Payload
Data Input Interface block, a Transmit Overhead Data
Input Interface block, a Transmit HDLC Controller, a
Transmit DS3/E3 Framer block and a Transmit LIU In-
terface Block which allows the Terminal Equipment to
transmit data to a remote terminal.
The Receive Sections, consist of a Receive LIU Inter-
face, a Receive DS3/E3 Framer, a Receive HDLC
Controller, a Receive Payload Data Output Interface,
and a Receive Overhead Data Interface which allows
the local terminal equipment to receive data from re-
mote terminal equipment.
The Microprocessor Interface is used to configure the
Framer in different operating modes and monitor the
performance of the Framer.
The Performance Monitor Sections consist of a large
number of Reset-upon-Read and Read-Only regis-
ters that contain cumulative and One-Second statis-
tics that reflect the performance/health of the three
channels of the Framer IC/system.
FEATURES
• Transmits, Receives and Processes data in the
DS3-C-bit Parity, DS3-M13, E3-ITU-T G.751 and
E3-ITU-T G.832 Framing Formats.
• 3 Channel HDLC Controller - Tx and Rx
• Interfaces to all Popular Microprocessors
• Integrated Framer Performance Monitor
• Available in a 272 Ball PBGA package
• 3.3V Power Supply, 5V Tolerant I/O
• Operating Temperature -40°C to +85°C
APPLICATIONS
• Network Interface Units
• CSU/DSU Equipment.
• PCM Test Equipment
• Fiber Optic Terminals
• DS3/E3 Frame Relay Equipment
FIGURE 1. BLOCK DIAGRAM OF THE XRT72L53
TestMode
NibbleLnTF
TxOHEnable
TxOHClk
TxOHFrame
TxAISEn
TxOH
TxOHIns
T3/E3
Transmit
Overhead
Interface
TxLineClk[n:0]
TxPOS[n:0]
TxNEG[n:0]
RxLineClk[n:0]
RxPOS[n:0]
RxNEG[n:0]
ExtLOS
RxOHEnable[n:0]
RxOHClk[n:0]
RxOH[n:0]
RxRed[n:0]
RxOHFrame[n:0]
RxOOF[n:0]
LIU
Interface/
Controller
T3/E3
Receive
Overhead
Interface
Typical Channel n
Where n = 0, 1 & 2
T3/E3 Transmit
Framer
T3/E3
transmit
Input
T3 FEAC & Data
Link Controller
Performance
Monitor
Interrupt
Controller
T3/E3 Receive
Framer
T3/E3
Receive
Output
HDLC
controller
uP
Interface
HDLC
controller
TxOHInd[n:0]
TxNibFrame[n:0]
TxFrame[n:0]
TxNibClk[n:0]
TxLnClk[n:0]
TxFrameRef[n:0]
TxNib[n:0]
TxSer[n:0]
A(11:0)
D(7:0)
ALE_AS
WR_R/W
CS
RDY_DTCK
Reset
INT
MOTO
RD_DS
RxClk[n:0]
RxOHind[n:0]
RxFrame[n:0]
RxNib[n:0]
RxSer[n:0]
RxOUTClk[n:0]
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
áç
PRELIMINARY
PIN DESCRIPTION CONNECTED PINS
PIN #
A13
PIN NAME
RxOHFrame[0]/
RxHDLCDat4[0]
A14 TxOHClk[0]
A15 TxOH[0]/
TYPE
O
O
I
DESCRIPTION
Receive Overhead Frame Boundary Indicator/Receive HDLC Con-
troller Data Output - Bit 4
The exact functionality of this output pin depends upon whether Chan-
nel 0 has been configured to operate in the “High Speed HDLC Control-
ler” Mode, or not.
Non-High Speed HDLC Controller Mode - Receive Overhead Frame
Boundary Indicator:
This output pin pulses "High" whenever the Receive Overhead Data
Output Interface” block outputs the first overhead bit (or nibble) of a new
DS3 or E3 frame.
High Speed HDLC Controller Mode - Receive HDLC Data Output -
Bit 4:
This pin functions as bit 4, within the byte-wide Receive HDLC Control-
ler output interface (RxHDLCDat[7:0]), whenever Channel 0 has been
configured to operate in the “High Speed HDLC Controller” Mode.
Transmit Overhead Clock output - Channel 0:
This output signal serves two purposes:
1. The Transmit Overhead Data Input Interface block will provide a rising
clock edge on this signal, one bit-period prior to the start to the instant
that the “Transmit Overhead Data Input Interface” block (associated with
Channel 1) is processing an overhead bit.
2. The Transmit Overhead Data Input Interface will sample the data at
the “TxOH[0]” input pin, on the falling edge of this clock signal (provided
that the “TxOHIns[0]” input pin is “HIGH”).
NOTE: The Transmit Overhead Data Input Interface block will supply a
clock edge for all overhead bits within the DS3 or E3 frame (via the
“TxOHClk[0]” output signal). This includes those overhead bits that the
“Transmit Overhead Data Input Interface” will not accept from the Termi-
nal Equipment.
Transmit Overhead Input Pin/Transmit HDLC Controller Data Input
- Bit 5 (Channel 0):
The exact functionality of this input pin depends upon whether Channel
0 has been configured to operate in the “High-Speed HDLC Controller”
Mode, or not.
TxHDLCDat5[0]
Non-High Speed HDLC Controller Mode - Transmit Overhead Input
pin - Channel 0:
The Transmit Overhead Data Input Interface accepts the overhead data
via this input pin, and inserts into the overhead bit position within the
very next outbound DS3 or E3 frame. If the TxOHIns pin is pulled
"High", then the Transmit Overhead Data Input Interface will sample the
data at this input pin (TxOH[0]), on the falling edge of the TxOHClk[0]
output pin. Conversely, if the TxOHIns[0] pin is pulled "Low", then the
Transmit Overhead Data Input Interface will NOT sample the data at this
input pin (TxOH[0]). Consequently, this data will be ignored.
High Speed HDLC Controller Mode - Transmit HDLC Data Input -
Bit 5:
This pin functions as bit 5, within the byte-wide Transmit HDLC Control-
ler input interface (TxHDLCDat[7:0]), whenever Channel 0 has been
configured to operate in the “High Speed HDLC Controller” Mode.
5
5 Page 
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
áç
PRELIMINARY
PIN DESCRIPTION CONNECTED PINS
PIN #
C6
PIN NAME
TAOS[0]
C7 LLOOP[0]
C8 RLOL[1]
C9 DMO[0]
C10 RxOHFrame[1]/
RxHDLCDat4[1]
C11 TxOHEnable[1]/
TxHDLCDat7[1]
TYPE
O
O
I
I
O
O
I
DESCRIPTION
Transmit All Ones Signal (TAOS) Command Input - Channel 0 (for
the DS3/E3 LIU IC):
This output pin is intended to be connected to the TAOS input pin of the
DS3/E3 Line Interface Unit IC. The user can control the state of this out-
put pin by writing a '0' or '1' to Bit 4 (TAOS) of the Line Interface Drive
Register (Address = 0x80). If the user commands this signal to toggle
"High" then it will force the Line Interface Unit IC to transmit an "All
Ones" pattern onto the line. Conversely, if the user commands this out-
put signal to toggle "Low" then the DS3/E3 Line Interface Unit IC will
proceed to transmit data based upon the pattern that it receives via the
TxPOS[0] and TxNEG[0] output pins.
Writing a "1" to Bit 4 of the Line Interface Drive Register (Address =
0x80) will cause this output pin to toggle "High". Writing a "0" to this bit-
field will cause this output pin to toggle "Low".
If the customer is not using an Exar “XRT73L0X Family of DS3/E3 LIU
ICs then this output pin can be used for a variety of other purposes.
Local Loopback Output Pin - Channel 0 (to be connected to the
DS3/E3 Line Interface Unit IC):
This output pin is intended to be connected to the LLOOP input pin of
the DS3/E3 LIU IC. The user can command this signal to toggle "High"
and, in turn, force the LIU into the Local Loopback mode.
Writing a "1" to bit 1 of the Line Interface Drive Register (Address =
0x80) will cause this output pin to toggle "High". Writing a "0" to this bit-
field will cause the RLOOP output to toggle "Low".
NOTE: This output pin can be used as a General Purpose Output.
Receive Loss of Lock Indicator input - Channel 1 (from the DS3/E3
LIU IC):
See Description for Pin B8
Drive Monitor Output Input pin - Channel 0 (from the DS3/E3 Line
Interface Unit IC):
This input pin is intended to be tied to the DMO output pin of the DS3/
E3 Line Interface Unit IC. The user can determine the state of this input
pin by reading Bit 2 (DMO) within the Line Interface Scan Register
(Address = 0x81). If this input signal is "High", then it means that the
drive monitor circuitry (within the DS3/E3 Line Interface Unit IC) has not
detected any bipolar signals at the MTIP and MRING inputs within the
last 128 (32 bit-periods. If this input signal is "Low", then it means that
bipolar signals are being detected at the MTIP and MRING input pins of
the DS3/E3 LIU device.
NOTE: This input pin can be used as a General Purpose Input pin.
Receive Overhead Frame Boundary Indicator/Receive HDLC Con-
troller Data Output - Bit 4; Channel 1:
See Description for Pin A13
Transmit Overhead Data Input Enable/Transmit HDLC Controller
Data Output - Bit 7; Channel 1:
See Description for Pin B14
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet XRT72L53.PDF ] | |
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