|
|
PDF 95MS18 Data sheet ( Hoja de datos )
| Número de pieza | 95MS18 | |
| Descripción | NM95MS18 | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 95MS18 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
July 1998
NM95MS18
Plug & Play Front-end device for ISA-Bus Systems
(Supports Windows®-NT, UNIX® and legacy systems)
General Description
The NM95MS18 is an industry standard ISA Plug-n-Play control-
ler that also supports Non-Plug-n-Play platforms like DOS,
WIN3.1x, Windows-NT and Unix.
In additon to being completely compliant to ISA PnP Specification
(Ver 1.0a), NM95MS18 integrates a total of 4Kbit of onchip
EEPROM for both PnP Resource data as well as non-PnP
configuration data to provide a true single chip solution.
NM95MS18 supports one logical device offering a flexible choice
of DMA, Interrupt and I/O address decoding features within a
single chip. NM95MS18 is implemented using Fairchild’s Ad-
vanced CMOS process and operates on a single power supply.
Features
s Fully compliant with industry standard ISA PnP specification
(Ver. 1.0a)
s Supports Non-PnP platforms like WINDOWS-NT, UNIX,
DOS/WIN3.1x
— No configuration utilities needed
s Supports Non-PnP "legacy" mode
— Can be programmed to power-up in 31 settings
s On-chip "Write-Protected" EEPROM for:
— PnP Resource data (2Kbits)
— 31 Power-on "legacy" configurations (2Kbits)
s Two modes of operation:
— DMA Mode
— Extended Interrupt Mode (supports PC-97 requirements)
s Configurable Interrupt types:
— TTL O/P
— Open Drain O/P
s Supports Wire-AND I/O chipselects
s Fully compatible with NM95MS16
s Available in 52-Pin PLCC Package
Block Diagram
ISA BUS
RSTDRV
From Switches
NPNP
SW[0:4]
Input Sense
Logic
Test Mode
Logic
SA[0:11]
IORD
IOWR
AEN
OSC
PnP Cycle
Detection
Logic
IRQOUT[0:7]
SD[0:7]
ISADRQ[0:1]
ISADACK[0:1]
SA[0:15]
IORD
IOWR
AEN
Data
Buffer
State
Machine
Registers
EEPROM
Controller
I/F
IRQ IRQIN[0:1]
Switch Logic
DMA
Switch
Logic
DRQIN
DACKOUT
ADDRESS
DECODER
IOCS[0:2]
DS500033-1
© 1998 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
1 page  
Timing Diagrams
AEN
SA[0:15]
IORD*
IOWR*
READ DATA
SD[0:7]
WRITE DATA
SD[0:7}
SA[0:15]
IOCS[0:1]*
(addr decode only)
IORD*
IOWR*
IOCS[0:1]*
(Qualfied with CMD)
Timings for ISA Read/Write Cycle
tAEN
tAC
VALID ADDRESS
tRVD
tAH
tRDH
VALID
tWD
tWDH
Decode Delay for Chipselect Generation
tCSA
VALID ADDRESS
DS500033-3
tCSA
tCSC
tCSC
Propagation Delay for IRQ/DRQ/DACK
DS500033-4
IRQ in
DRQ in
ISADACK
IRQ out
DRQ out
DACKOUT
tIDD
tIDD
DS500033-5
INTRODUCTION
NM95MS18 supports both Plug-n-Play platforms (PC with WIN-
DOWS-95 and/or PnP BIOS) as well as Non-Plug-n-Play plat-
forms (PC with WINDOWS-NT, Win3.x/DOS and Non-PnP BIOS).
The choice of interface (PnP or Non-PnP) is selected by using a
single pin (N_PnP*). Under PnP interface, NM95MS18 is fully
compliant with ISA Plug-n-Play specification (Ver 1.0a) and is
functionally compatible to its predecessor NM95MS16. Under
Non-P 'n' P interface, NM95MS18 powers-up active with a prede-
termined configuration eliminating any need for an external PnP
configuration support. Five external inputs to NM95MS18 allows
to choose the default power-up configuration from 31 different
predetermined configurations. NM95MS18 integrates 2 kbits of
on-board EEPROM to store all the 31 configuration information as
well as an additional 2 kbits EEPROM area to store standard PnP
resource information. Entire memory can be write protected.
NM95MS18 also allows ISA interrupts to be shared.
5 www.fairchildsemi.com
5 Page 
Internal EEPROM Memory of
NM95MS18 (Continued)
resource allocation probabilities and also allows presence of
multiple cards of the same type. Each IRQOUTx signal can be
individually set for either Interrupt type and this is done by setting
Details of timing information for Microwire protocol can be ob-
tained from Fairchild’s Microwire EEPROM Datasheets. Please
appropriate bits in EEPROM register. Refer the USER’S GUIDE
for more detail.
refer NM93C66 datasheet. This datasheet can be downloaded
from Fairchild’s home page on World-Wide-Web. (http://
Wire-ANDing of I/O Chipselects
www.fairchildsemi.com)
The IOCS1* and IOCS2* signals can be internally Wire-ANDed
with IOCS0* signal on NM95MS18. When this feature is enabled,
SHARING OF INTERRUPTS
IOCS0* signal can also act as “Output Enable” signal for ISA bus
Interrupt output (IRQOUTx) signals from NM95MS18 can be
configured as either standard TTL type or Open-Drain type.
Interrupt outputs configured as Open-Drain type can share an
interrupt on the ISA bus. Sharing of interrupt increases ISA bus
data buffers eliminating extra glue logic on the board. Setting
appropriate bits in EEPROM register enables this feature. Refer
the USER’S GUIDE for more detail. Following diagram illustrates
this feature.
WIRE-ANDing of I/O Chipselects
,,,SA[0:15]
IORD*/IOWR
Base Address
for IOCS0
Base Address
for IOCS1
Base Address
for IOCS2
IOCS0*
IOCS1*
IOCS2*
IOCS1* Wire-ANDed
with IOCS0*
IOCS2* Wire-ANDed
with IOCS0*
Note 1: This illustratory waveform assumes that both IOCS1* and IOCS2* are set to be Wire-ANDed with IOCS0*. They can also be set individually.
Note 2: In this waveform, IOCSx* are set to be decoded off of address and IORD*/IOWR.
Note 3: Refer “I/O DECODE QUALIFICATION REGISTER” description for more information.
DS500033-11
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 95MS18.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 95MS18 | NM95MS18 | Fairchild Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |