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PDF STR91xFA Data sheet ( Hoja de datos )
| Número de pieza | STR91xFA | |
| Descripción | 32-bit Flash Microcontrollers | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STR91xFA
ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN,
AC motor control, 4 timers, ADC, RTC, DMA
PRELIMINARY DATA
Features
www.DataSheet4U.com
■ 16/32-bit 96 MHz ARM9E based MCU
– ARM966E-S RISC core: Harvard archi-
tecture, 5-stage pipeline, Tightly-Coupled
Memories (SRAM and Flash)
– STR91xFA implementation of core adds
high-speed burst Flash memory interface,
instruction prefetch queue, branch cache
– Up to 96 MIPS directly from Flash memory
– Single-cycle DSP instructions are supported
– Binary compatible with 16/32-bit ARM7 code
■ Dual burst Flash memories, 32-bits wide
– 256KB/512KB Main Flash, 32KB 2nd Flash
– Sequential Burst operation up to 96 MHz
– 100K min erase cycles, 20 yr min retention
■ SRAM, 32-bits wide
– 64K or 96K bytes, optional battery backup
■ 9 programmable DMA channels
– One for Ethernet, 8 programmable channels
■ Clock, reset, and supply management
– Two supplies required. Core: 1.8 V +/-10%,
I/O: 2.7 to 3.6 V
– Internal oscillator operating with external
4-25 MHz crystal
– Internal PLL up to 96MHz
– Real-time clock provides calendar functions,
tamper detection, and wake-up functions
– Reset Supervisor monitors voltage supplies,
watchdog timer, wake-up unit, ext. reset
– Brown-out monitor for early warning interrupt
– Run, Idle, and Sleep Mode as low as 50 uA
■ Operating temperature -40 to +85°C
■ Vectored interrupt controller (VIC)
– 32 IRQ vectors, 30 intr pins, any can be FIQ
– Branch cache minimizes interrupt latency
■ 8-channel, 10-bit A/D converter (ADC)
– 0 to 3.6V range, 0.7 usec conversion
– DMA capability
LQFP80 12 x12mm
LQFP128 14 x 14mm
LFBGA144 10 x 10 x 1.7
■ 10 Communication interfaces
– 10/100 Ethernet MAC with DMA and MII port
– USB Full-speed (12 Mbps) slave device
– CAN interface (2.0B Active)
– 3 16550-style UARTs with IrDA protocol
– 2 Fast I2C™, 400 kHz
– 2 channels for SPI™, SSI™, or Microwire™
■ External Memory Interface (EMI)
– 8- or 16-bit data
– Up to 24-bit addressing
– Static Async modes for LQFP128 packages
– Additional Burst Synchronous modes for
LFBGA144 packages
■ Up to 80 I/O pins (muxed with interfaces)
– 5 V tolerant, 16 have high sink current
(8 mA)
– Bit-wise manipulation of pins within a port
■ 16-bit standard timers (TIM)
– 4 timers each with 2 input capture, 2 output
compare, PWM and pulse count modes
■ 3-Phase induction motor controller (IMC)
– 3 pairs of PWM outputs, adjustable centers
– Emergency stop, dead-time gen, tach input
■ JTAG interface with boundary scan
– ARM EmbeddedICE® RT for debugging
– In-System Programming (ISP) of Flash
■ Embedded trace module (ARM ETM9)
– Hi-speed instruction tracing, 9-pin interface
May 2007
Rev 1
1/78
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without noticwew. w.st.com
78
1 page  
STR91xFA
6.11
6.12
6.13
6.14
6.15
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . 57
6.12.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . 58
6.12.4 Electro-Static Discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.5 Static and Dynamic Latch-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.6 Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . 58
6.12.7 Electrical Sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
External memory bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Communication interface electrical characteristics . . . . . . . . . . . . . . . . . . . . 65
6.15.1 10/100 Ethernet MAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 65
6.15.2 USB electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.15.3 CAN interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.15.4 I2C electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.15.5 SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5/78
5 Page 
STR91xFA
Functional overview
Flash memories are programmed half-word (16 bits) at a time, but are erased by sector or by
full array.
2.7.1
Primary Flash memory
Using the STR91xFA device configuration software tool and 3rd party Integrated Developer
Environments, it is possible to specify that the primary Flash memory is the default memory
from which the CPU boots at reset, or otherwise specify that the secondary Flash memory is
the default boot memory. This choice of boot memory is non-volatile and stored in a location
that can be programmed and changed only by JTAG In-System Programming. See Section 5:
Memory mapping, for more detail.
The primary Flash memory has equal length 64K byte sectors. Devices with 256 Kbytes of
primary Flash have four sectors and 512K devices have eight sectors.
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2.7.2
Secondary Flash memory
The smaller of the two Flash memories can be used to implement a bootloader, capable of
storing code to perform robust In-Application Programming (IAP) of the primary Flash memory.
The CPU executes code from the secondary Flash, while updating code in the primary Flash
memory. New code for the primary Flash memory can be downloaded over any of the
interfaces on the STR91xFA (USB, Ethernet, CAN, UART, etc.)
Additionally, the Secondary Flash memory may also be used to store small data sets by
emulating EEPROM though firmware, eliminating the need for external EEPROM memories.
This raises the data security level because passcodes and other sensitive information can be
securely locked inside the STR91xFA device.
The secondary Flash memory is 32 Kbytes and has four equal length sectors of 8 Kbytes each.
Both the primary Flash memory and the secondary Flash memory can be programmed with
code and/or data using the JTAG In-System Programming (ISP) channel, totally independent of
the CPU. This is excellent for iterative code development and for manufacturing.
2.8 One-time-programmable (OTP) memory
There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory
calibration constants, or other permanent data constants. These OTP data bytes can be
programmed only one time through either the JTAG interface or by the CPU, and these bytes
can never be altered afterwards. As an option, a “lock bit” can be set by the JTAG interface or
the CPU which will block any further writing to the this OTP area. The “lock bit” itself is also
OTP. If the OTP array is unlocked, it is always possible to go back and write to an OTP byte
location that has not been previously written, but it is never possible to change an OTP byte
location if any one bit of that particular byte has been written before. The last two OTP bytes are
reserved for the STR91xFA product ID and revision level.
2.8.1
Product ID and revision level
OTP bytes 31 and 30 are programmed at ST factory before shipment and may be read by
firmware to determine the STR91xFA product type and silicon revision so it can optionally take
action based on the silicon on which it is running. Byte 31 contains the the major family
identifier of "9" (for STR9) in the high-nibble location, and the minor family identifier in the low-
nibble location. Today the low-nibble contains "1", but future family members may have other
11/78
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STR91xFA.PDF ] | |
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