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PDF HI5905 Data sheet ( Hoja de datos )
| Número de pieza | HI5905 | |
| Descripción | A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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March 2003
HI5905
FN4259.4
14-Bit, 5MSPS A/D Converter
The HI5905 is a monolithic, 14-bit, 5MSPS Analog-to-
Digital Converter fabricated in an advanced BiCMOS
process. It is designed for high speed, high resolution
applications where wide bandwidth, low power
consumption and excellent SINAD performance are
essential. With a 100MHz full power input bandwidth and
high frequency accuracy, the converter is ideal for many
types of communication systems employing digital IF
architectures.
The HI5905 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold amplifier (S/H). The HI5905 has excellent
dynamic performance while consuming 350mW power at
5MSPS.
Data output latches are provided which present valid data to
the output bus with a low data latency of 4 clock cycles.
Part Number Information
PART
TEMP. RANGE
NUMBER (oC) PACKAGE
PKG.
NO.
HI5905IN
-40 to 85 44 Ld MQFP Q44.10x10
HI5905EVAL2
25 Low Frequency Eval Platform
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MSPS
• Low Power at 5MSPS . . . . . . . . . . . . . . . . . . . . . .350mW
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• SINAD at 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . >70dB
• Low Data Latency
• Internal Voltage Reference
• TTL Compatible Clock Input
• CMOS Compatible Digital Data Outputs
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Asymmetric Digital Subscriber Line (ADSL)
• Document Scanners
• Reference Literature
- AN9214, Using Intersil High Speed A/D Converters
- AN9785, Using the Intersil HI5905 EVAL2 Evaluation
Board
Pinout
HI5905 (MQFP)
TOP VIEW
NC
NC
DGND1
NC
AVCC
AGND
NC
NC
VIN+
VIN-
VDC
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
D3
D4
D5
D6
D7
NC
DVCC2
DGND2
D8
D9
NC
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
Timing Waveforms
ANALOG
INPUT
HI5905
CLOCK
INPUT SN - 1 HN - 1 SN
HN SN + 1 HN + 1 SN + 2 HN + 2 SN + 3 HN + 3 SN + 4 HN + 4 SN + 5 HN + 5 SN + 6 HN + 6
INPUT
S/H
1ST
STAGE
B1, N - 1
B1, N
B1, N + 1
B1, N + 2
B1, N + 3
B1, N + 4
B1, N + 5
2ND
STAGE
3RD
STAGE
4TH
STAGE
B2, N - 2
B2, N - 1
B2, N
B2, N + 1
B2, N + 2
B2, N + 3
B2, N + 4
B3, N - 2
B3 , N - 1
B3, N
B3, N + 1
B3, N + 2
B3, N + 3
B3, N + 4
B4, N - 3
B4, N - 2
B4, N - 1
B4, N
B4, N + 1
B4, N + 2
B4, N + 3
5TH
STAGE
DATA
OUTPUT
B5, N - 3
DN - 4
NOTES:
4. SN: N-th sampling period.
5. HN: N-th holding period.
B5, N - 2
B5, N - 1
B5, N
B5, N + 1
B5, N + 2
B5, N + 3
DN - 3
DN - 2
DN - 1
DN
DN + 1
DN + 2
tLAT
6. BM, N: M-th stage digital output corresponding to N-th sampled
input.
7. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG
INPUT
tAP
tAJ
CLOCK
INPUT
1.5V
1.5V
DATA
OUTPUT
DATA N-1
tOD
tH
3.5V
1.5V
DATA N
FIGURE 2. INPUT-TO-OUTPUT TIMING
5
5 Page 
HI5905
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sinewave.
The input sinewave has an amplitude which swings from -fS
to +fS. The bandwidth given is measured at the specified
sampling frequency.
Timing Definitions
Refer to Figure 1, Internal Circuit Timing, and Figure 2,
Input-To-Output Timing, for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is still valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the digital data is output on
the bus at the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input sample by 4
clock cycles.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HI5905.PDF ] | |
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