|
|
PDF HI5762 Data sheet ( Hoja de datos )
| Número de pieza | HI5762 | |
| Descripción | A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HI5762 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
TM
Data Sheet
HI5762
February 1999 File Number 4318.2
Dual 10-Bit, 60MSPS A/D Converter with
Internal Voltage Reference
The HI5762 is a monolithic, dual 10-bit, 60MSPS analog-to-
digital converter fabricated in an advanced CMOS process.
It is designed for high speed applications where integration,
bandwidth and accuracy are essential. Built by combining
two cores of the HI5767 single channel 10-bit 60MSPS
analog-to-digital converter, the HI5762 reaches a new level
of multi-channel integration. The fully pipeline architecture
and an innovative input stage enable the HI5762 to accept a
variety of input configurations, single-ended or fully
differential. Only one external clock is necessary to drive
both converters and an internal band-gap voltage reference
is provided. This allows the system designer to realize an
increased level of system integration resulting in decreased
cost and power dissipation.
The HI5762 has excellent dynamic performance while
consuming only 650mW of power at 60MSPS. The A/D only
requires a single +5V power supply and encode clock. Data
output latches are provided which present valid data to the
output bus with a latency of 6 clock cycles.
For those customers needing dual channel 8-bit resolution,
www.DataSheet4U.com
please refer to the HI5662. For single channel 10-bit
applications, please refer to the HI5767.
Ordering Information
PART
NUMBER
HI5762/6IN
HI5762EVAL2
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
-40 to 85 44 Ld MQFP
Q44.10x10
25 Evaluation Platform
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .60MSPS
• 8.8 Bits at fIN = 10MHz
• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . 650mW
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz
• Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB
• On-Chip Sample and Hold Amplifiers
• Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V
• Fully Differential or Single-Ended Analog Inputs
• Single Supply Voltage Operation . . . . . . . . . . . . . . . . +5V
• TTL/CMOS Compatible Sampling Clock Input
• CMOS Compatible Digital Outputs . . . . . . . . . . . . 3.0/5.0V
• Offset Binary Digital Data Output Format
• Dual 10-Bit A/D Converters on a Monolithic Chip
Applications
• Wireless Local Loop
• PSK and QAM I&Q Demodulators
• Medical Imaging
• High Speed Data Acquisition
Pinout
HI5762 (MQFP)
TOP VIEW
AGND
AVCC2
ID9
ID8
ID7
ID6
ID5
DVCC3
DGND
ID4
ID3
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
AGND
AVCC2
QD9
QD8
QD7
QD6
QD5
DVCC3
DGND
QD4
QD3
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1 page  
HI5762
Absolute Maximum Ratings TA = 25oC
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Operating Conditions
Temperature Range
HI5762/6IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
HI5762/6IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN TYP MAX
ACCURACY
Resolution
10 -
-
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = 10MHz
fIN = 10MHz
- 2-
- ±0.4 ±1.0
Offset Error, VOS
Full Scale Error, FSE
DYNAMIC CHARACTERISTICS
fIN = DC
fIN = DC
-40 - +40
-4-
Minimum Conversion Rate
No Missing Codes
-1-
Maximum Conversion Rate
No Missing Codes
60 -
-
Effective Number of Bits, ENOB
Signal to Noise and Distortion Ratio, SINAD
= R-----M-----S------NR----oM---i--sS---e---S--+--i-g--D--n--i-as---lt--o---r--t--i-o----n-
fIN = 10MHz
fIN = 10MHz
8.4 8.8
- 54.7
-
-
Signal to Noise Ratio, SNR
= R-R----M-M----S-S-----SN----i-og---in-s---ae---l
fIN = 10MHz
- 54.7 -
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
I/Q Channel Crosstalk
I/Q Channel Offset Match
I/Q Channel Full Scale Error Match
Transient Response
Over-Voltage Recovery
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input
Range (VIN+ - VIN-)
Maximum Peak-to-Peak Single-Ended
Analog Input Range
fIN = 10MHz
fIN = 10MHz
fIN = 10MHz
fIN = 10MHz
f1 = 1MHz, f2 = 1.02MHz
(Note 2)
0.2V Overdrive (Note 2)
- -68 -
- -70 -
- -73 -
- 70 -
- 64 -
- -75 -
- 10 -
- 10 -
-1-
-1-
- ±0.5 -
- 1.0 -
UNITS
Bits
LSB
LSB
LSB
LSB
MSPS
MSPS
Bits
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
LSB
LSB
Cycle
Cycle
V
V
3-5
5 Page 
HI5762
As illustrated in the functional block diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a two-
bit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
analog sample is taken (see the timing diagram in Figure 1).
This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).
Internal Reference Voltage Output, VREFOUT
The HI5762 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is
required. VROUT must be connected to VRIN when using the
internal reference voltage.
An internal band-gap reference voltage followed by an
amplifier/buffer generates the precision +2.5V reference voltage
used by the converter. A band-gap reference circuit is used to
generate a precision +1.25V internal reference voltage. This
voltage is then amplified by a wide-band uncompensated
operational amplifier connected in a gain-of-two configuration.
An external, user-supplied, 0.1mF capacitor connected from
the VROUT output pin to analog ground is used to set the
dominant pole and to maintain the stability of the operational
amplifier.
Reference Voltage Input, VREFIN
The HI5762 is designed to accept a +2.5V reference voltage
source at the VRIN input pin. Typical operation of the
converter requires VRIN to be set at +2.5V. The HI5762 is
tested with VRIN connected to VROUT yielding a fully
differential analog input voltage range of ±0.5V.
The user does have the option of supplying an external +2.5V
reference voltage. As a result of the high input impedance
presented at the VRIN input pin, 1.25kΩ typically, the external
reference voltage being used is only required to source 2mA
of reference input current. In the situation where an external
reference voltage will be used an external 0.1µF capacitor
must be connected from the VROUT output pin to analog
ground in order to maintain the stability of the internal
operational amplifier.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, VRIN .
Analog Input, Differential Connection
The analog input of the HI5762 is a differential input that can
be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 16 and Figure 17) will deliver
the best performance from the converter.
VIN
-VIN
I/QIN+
R HI5762
I/QVDC
R
I/QIN-
FIGURE 16. AC COUPLED DIFFERENTIAL INPUT
Since the HI5762 is powered by a single +5V analog supply,
the analog input is limited to be between ground and +5V.
For the differential input connection this implies the analog
input common mode voltage can range from 0.25V to 4.75V.
The performance of the ADC does not change significantly
with the value of the analog input common mode voltage.
A DC voltage source, I/QVDC, equal to 3.0V (typical), is
made available to the user to help simplify circuit design
when using an AC coupled differential input. This low output
impedance voltage source is not designed to be a reference
but makes an excellent DC bias source and stays well within
the analog input common mode voltage range over
temperature.
For the AC coupled differential input (Figure 16) and with VRIN
connected to VROUT, full scale is achieved when the VIN and
-VIN input signals are 0.5VP-P, with -VIN being 180 degrees
out of phase with VIN. The converter will be at positive full
scale when the I/QIN+ input is at VDC + 0.25V and the I/QIN-
input is at VDC - 0.25V (I/QIN+ - I/QIN- = +0.5V). Conversely,
the converter will be at negative full scale when the I/QIN+
input is equal to VDC - 0.25V and I/QIN- is at
VDC + 0.25V (I/QIN+ - I/QIN- = -0.5V).
3-11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HI5762.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HI5760 | A/D Converter | Intersil Corporation |
| HI5762 | A/D Converter | Intersil Corporation |
| HI5766 | A/D Converter | Intersil Corporation |
| HI5767 | A/D Converter | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |