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SCANPSC110F PDF даташит

Спецификация SCANPSC110F изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port».

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Номер произв SCANPSC110F
Описание SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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SCANPSC110F Даташит, Описание, Даташиты
March 1993
Revised August 2000
SCANPSC110F
SCAN Bridge Hierarchical and Multidrop Addressable
JTAG Port (IEEE1149.1 System Test Support)
General Description
The SCANPSC110F Bridge extends the IEEE Std. 1149.1
test bus into a multidrop test bus environment. The advan-
tage of a hierarchical approach over a single serial scan
chain is improved test throughput and the ability to remove
a board from the system and retain test access to the
remaining modules. Each SCANPSC110F Bridge supports
up to 3 local scan rings which can be accessed individually
or combined serially. Addressing is accomplished by load-
ing the instruction register with a value matching that of the
Slot inputs. Backplane and inter-board testing can easily
be accomplished by parking the local TAP Controllers in
one of the stable TAP Controller states via a Park instruc-
tion. The 32-bit TCK counter enables built in self test oper-
ations to be performed on one port while other scan chains
are simultaneously tested.
Features
s True IEEE1149.1 hierarchical and multidrop addressable
capability
s The 6 slot inputs support up to 59 unique addresses, a
Broadcast Address, and 4 Multi-cast Group Addresses
s 3 IEEE 1149.1-compatible configurable local scan ports
s Mode Register allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
s 32-bit TCK counter
s 16-bit LFSR Signature Compactor
s L4
s local TAPs can be 3-stated via the OE input to allow an
alternate test master to take control of the local TAPs
Ordering Code:
Order Number Package Number
Package Description
SCANPSC110FSC
M28B
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin
Names
Description
TCKB
TMSB
TDIB
TDOB
TRST
Backplane Test Clock Input
Backplane Test Mode Select Input
Backplane Test Data Input
Backplane Test Data Output
Asynchronous Test Reset Input (Active LOW)
S(0,5)
OE
Address Select Port
Local Scan Port Output Enable (Active LOW)
TCKL(13) Local Port Test Clock Output
TMSL(13) Local Port Test Mode Select Output
TDIL(13) Local Port Test Data Input
TDOL(13) Local Port Test Data Output
© 2000 Fairchild Semiconductor Corporation DS011570
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SCANPSC110F Даташит, Описание, Даташиты
TABLE 1. Glossary of Terms
LFSR
Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test
data.
LSP
Local
Local Scan Port. A four signal port that drives a local(i.e. non-backplane) scan chain.
(e.g., TCKL1, TMSL1, TDOL1, TDIL1)
Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANPSC110F Bridge Test
Access Port that drives them. The term localwas adopted from the system test architecture that the
SCANPSC110F Bridge will most commonly be used in; namely, a system test backplane with a
SCANPSC110F Bridge on each card driving up to 3 localscan rings per card. (Each card can contain
multiple SCANPSC110Fs, with 3 local scan ports per SCANPSC110F.)
Park/Unpark
Park, parked, unpark, and unparked, are used to describe the state of the LSP controller and the state
of the local TAP controllers (the local TAP controllersrefers to the TAP controllers of the scan compo-
nents that make up a local scan ring). Park is also used to describe the action of parking a LSP (transi-
tioning into one of the Parked LSP controller states). It is important to understand that when a LSP
controller is in one of the parked states, TMSL is held constant, thereby holding or parkingthe local
TAP controllers in a given state.
TAP Test Access Port as defined by IEEE Std. 1149.1
Selected/Unselected Selected and Unselected refers to the state of the SCANPSC110F Bridge Selection Controller. A
selected SCANPSC110F has been properly addressed and is ready to receive Level 2 protocol. Unse-
lected SCANPSC110Fs monitor the system test backplane, but do not accept Level 2 protocol (except
for the GOTOWAIT instruction). The data registers and LSPs of unselected SCANPSC110Fs are not
accessible from the system test master.
Active Scan Chain
The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given
moment. When a SCANPSC110F is selected with all of its LSPs parked, the active scan chain is the
current scan bridge register only. When a LSP is unparked, the active scan chain becomes: TDIB the
current SCANPSC110F register the local scan ring registers a PAD bit TDOB. Refer to Table 4
for Unparked configurations of the LSP network.
Level 1 Protocol
Level 1 is the protocol used to address a SCANPSC110F.
Level 2 Protocol
Level 2 is the protocol that is used once a SCANPSC110F is selected. Level 2 protocol is IEEE Std.
1149.1 compliant when an individual SCANPSC110F is selected.
PAD
A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit eliminates
the prop delay that would be added by the SCANPSC110F LSPN logic between TDILn and TDOL(n+1)
or TDOB by buffering and synchronizing the TDIL inputs to the falling edge of TCKB, thus allowing data
to be scanned at higher frequencies without violating set-up and hold times.
LSB
Least Significant Bit, the right-most position in a register (bit 0)
MSB
Most Significant Bit, the left-most position in a register
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SCANPSC110F Даташит, Описание, Даташиты
TABLE 2. Detailed Pin Description Table
Name
TMSB
TDIB
TDOB
TCKB
I/O (Note 1)
Pin #
(SOIC & LCC)
Description
TTL Input w/Pull-Up Resistor
10 BACKPLANE TEST MODE SELECT: Controls sequencing
through the TAP Controller of the SCANPSC110F Bridge. Also
controls sequencing of the TAPs which are on the three (3) local
scan chains.
TTL Input w/Pull-Up Resistor
12 BACKPLANE TEST DATA INPUT: All backplane scan data is
supplied to the SCANPSC110F through this input pin.
3-STATEable,
32 mA/64 mA Drive,
Reduced-Swing,
13 BACKPLANE TEST DATA OUTPUT: This output drives test data
from the SCANPSC110F and the local TAPs, back toward the scan
master controller.
Output
TTL Schmitt Trigger Input
11 TEST CLOCK INPUT FROM THE BACKPLANE: This is the mas-
ter clock signal that controls all scan operations of the
SCANPSC110F and of the three (3) local scan ports.
TRST
S(05)
TTL Input w/Pull-Up Resistor
TTL Inputs
9
2, 3, 4,
5, 6, 7
TEST RESET: An asynchronous reset signal (active LOW) which
initializes the SCANPSC110F logic.
SLOT IDENTIFICATION: The configuration of these six (6) pins is
used to identify (assign a unique address to) each SCANPSC110F
on the system backplane.
OE TTL Input
TDOL(13) 3-STATEable,
24 mA/24 mA
Drive Outputs
TDIL(13) TTL Inputs w/Pull-Up
Resistors
TMSL(13) 3-STATEable,
24 mA/24 mA
Drive Outputs
TCKL(13) 3-STATEable,
24 mA/24 mA
Drive Output
VCC
GND
Power Supply Voltage
Ground potential
1
15,19,
24
OUTPUT ENABLE for the Local Scan Ports, active LOW. When
HIGH, this active-LOW control signal 3-STATEs all three local scan
ports on the SCANPSC110F, to enable an alternate resource to
access one or more of the three (3) local scan chains.
TEST DATA OUTPUTS: Individual output for each of the three (3)
local scan ports.
18, 23,
27
16, 20,
25
17, 22,
26
8, 28
14, 21
TEST DATA INPUTS: Individual scan data input for each of the
three (3) local scan ports.
TEST MODE SELECT OUTPUTS: Individual output for each of the
three (3) local scan ports. TMSL does not provide a pull-up resistor
(which is assumed to be present on a connected TMS input, per
the IEEE 1149.1 requirement)
LOCAL TEST CLOCK OUTPUTS: Individual output for each of
the three (3) local scan ports. These are buffered versions of
TCKB.
Power supply pins, 5.0V ±10%.
Power supply pins 0V.
Note 1: All pins are active HIGH unless otherwise noted.
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