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SCANPSC110F PDF даташит

Спецификация SCANPSC110F изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port».

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Номер произв SCANPSC110F
Описание SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port
Производители National Semiconductor
логотип National Semiconductor логотип 

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SCANPSC110F Даташит, Описание, Даташиты
October 1999
SCANPSC110F
SCAN Bridge Hierarchical and Multidrop Addressable
JTAG Port (IEEE1149.1 System Test Support)
General Description
The SCANPSC110F Bridge extends the IEEE Std. 1149.1
test bus into a multidrop test bus environment. The advan-
tage of a hierarchical approach over a single serial scan
chain is improved test throughput and the ability to remove a
board from the system and retain test access to the remain-
ing modules. Each SCANPSC110F Bridge supports up to 3
local scan rings which can be accessed individually or com-
bined serially. Addressing is accomplished by loading the in-
struction register with a value matching that of the Slot in-
puts. Backplane and inter-board testing can easily be
accomplished by parking the local TAP Controllers in one of
the stable TAP Controller states via a Park instruction. The
32-bit TCK counter enables built in self test operations to be
performed on one port while other scan chains are simulta-
neously tested.
n The 6 slot inputs support up to 59 unique addresses, a
Broadcast Address, and 4 Multi-cast Group Addresses
n 3 IEEE 1149.1-compatible configurable local scan ports
n Mode Register allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
n 32-bit TCK counter
n 16-bit LFSR Signature Compactor
n Local TAPs can be tri-stated via the OE input to allow
an alternate test master to take control of the local TAPs
n The IP version of this device supports features not
described in this datasheet such as 8 slot inputs for
enhanced address capability and additional instructions.
For a completed description of the additional instructions
supported, refer to the SCANPSC110 supplemental
datasheet.
Features
n True IEEE1149.1 hierarchical and multidrop addressable
capability
Connection Diagrams
28-Pin
CDIP and Flatpak
Pin Assignment for LCC
DS100327-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100327
DS100327-2
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SCANPSC110F Даташит, Описание, Даташиты
Connection Diagrams (Continued)
Order Number
SCANPSC110FFMQB
SCANPSC110FDMQB
SCANPSC110FLMQB
Description
Military Flatpak
Military DIP
Military Leadless Chip Carrier
Pin Description
Names
TCKB
TMSB
TDIB
TDOB
TRST
Backplane Test Clock Input
Backplane Test Mode Select Input
Backplane Test Data Input
Backplane Test Data Output
Asynchronous Test Reset Input (Active low)
S(0,5)
OE
Address Select Port
Local Scan Port Output Enable (Active low)
TCKL(1–3)
TMSL(1–3)
TDIL(1–3)
TDOL(1–3)
Local Port Test Clock Output
Local Port Test Mode Select Output
Local Port Test Data Input
Local Port Test Data Output
Table of Contents
1. GLOSSARY OF TERMS: 2
2. DETAILED PIN DESCRIPTION TABLE: 3
3. OVERVIEW OF SCAN BRIDGE FUNCTIONS: 4
A. SCANPSC110F Bridge Architecture: 4
B. SCANPSC110F Bridge State Machines: 4
4. TESTER/SCANPSC110F BRIDGE INTERFACE: 8
5. REGISTER SET: 8
6. ADDRESSING SCHEME: 8
7. HIERARCHICAL TEST SUPPORT: 9
8. LEVEL 1 PROTOCOL: 9
A. Addressing Modes: 9
B. Direct Addressing: 10
C. Broadcast Addressing: 10
D. Multi-Cast Addressing: 10
9. LEVEL 2 PROTOCOL: 11
A. Level 2 Instruction Types: 11
B. Level 2 Instruction Descriptions: 12
10. REGISTER DESCRIPTIONS: 14
11. SPECIAL FEATURES: 16
A. BIST Support: 16
B. RESET: 16
C. Port Synchronization: 16
12. ABSOLUTE MAXIMUM RATINGS: 18
13. RECOMMENDED OPERATING CONDITIONS: 18
14. DC ELECTRICAL CHARACTERISTICS: 18
15. AC ELECTRICAL CHARACTERISTICS: 20
16. AC WAVEFORMS: 22
17. APPENDIX: 24
A. State Diagram for Boundary-Scan TAP Control-
ler: 24
18. APPLICATIONS EXAMPLE: 24
TABLE 1. Glossary of Terms
LFSR
LSP
Local
Park/Unpark
TAP
Selected/Unselected
Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial
test data.
Local Scan Port. A four signal port that drives a “local” (i.e. non-backplane) scan chain. (e.g.,
TCKL1, TMSL1, TDOL1, TDIL1)
Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANPSC110F Bridge
Test Access Port that drives them. The term “local” was adopted from the system test architecture
that the ’PSC110F Bridge will most commonly be used in; namely, a system test backplane with a
’PSC110F Bridge on each card driving up to 3 “local” scan rings per card. (Each card can contain
multiple ’PSC110Fs, with 3 local scan ports per ’PSC110F.)
Park, parked, unpark, and unparked, are used to describe the state of the LSP controller and the
state of the local TAP controllers (the “local TAP controllers” refers to the TAP controllers of the
scan components that make up a local scan ring). Park is also used to describe the action of
parking a LSP (transitioning into one of the Parked LSP controller states). It is important to
understand that when a LSP controller is in one of the parked states, TMSL is held constant,
thereby holding or “parking” the local TAP controllers in a given state.
Test Access Port as defined by IEEE Std. 1149.1
Selected and Unselected refers to the state of the ’PSC110F Bridge Selection Controller. A
selected ’PSC110F has been properly addressed and is ready to receive Level 2 protocol.
Unselected ’PSC110Fs monitor the system test backplane, but do not accept Level 2 protocol
(except for the GOTOWAIT instruction). The data registers and LSPs of unselected ’PSC110Fs are
not accessible from the system test master.
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SCANPSC110F Даташит, Описание, Даташиты
Table of Contents (Continued)
TABLE 1. Glossary of Terms (Continued)
Active Scan Chain
Level 1 Protocol
Level 2 Protocol
PAD
LSB
MSB
The Active Scan Chain refers to the scan chain configuration as seen by the test master at a given
moment. When a ’PSC110F is selected with all of its LSPs parked, the active scan chain is the
current scan bridge register only. When a LSP is unparked, the active scan chain becomes: TDIB
the current ’PSC110F register the local scan ring registers a PAD bit TDOB. Refer to
Table 4 for Unparked configurations of the LSP network.
Level 1 is the protocol used to address a ’PSC110F.
Level 2 is the protocol that is used once a ’PSC110F is selected. Level 2 protocol is IEEE Std.
1149.1 compliant when an individual ’PSC110F is selected.
A one bit register that is placed at the end of each local scan port scan-chain. The PAD bit
eliminates the prop delay that would be added by the ’PSC110F LSPN logic between TDILn and
TDOL(n+1) or TDOB by buffering and synchronizing the TDIL inputs to the falling edge of TCKB,
thus allowing data to be scanned at higher frequencies without violating set-up and hold times.
Least Significant Bit, the right-most position in a register (bit 0)
Most Significant Bit, the left-most position in a register
Name
I/O (Note 1)
TMSB
TDIB
TDOB
TCKB
TRST
S(0–5)
OE
TTL Input w/Pull-Up
Resistor
TTL Input w/Pull-Up
Resistor
TRI-STATEable,
32 mA/64 mA Drive,
Reduced-Swing,
Output
TTL Schmitt Trigger
Input
TTL Input w/Pull-Up
Resistor
TTL Inputs
TTL Input
TDOL(1–3) TRI-STATEable,
24 mA/24 mA
Drive Outputs
TDIL(1–3) TTL Inputs w/Pull-Up
Resistors
TMSL(1–3) TRI-STATEable,
24 mA/24 mA
Drive Outputs
TCKL(1–3) TRI-STATEable,
24 mA/24 mA
Drive Output
VCC Power Supply Voltage
TABLE 2. Detailed Pin Description Table
Pin #
(SOIC
& LCC)
10
12
13
Description
BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP
Controller of the SCANPSC110F Bridge. Also controls sequencing of the TAPs
which are on the three (3) local scan chains.
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the
’PSC110F through this input pin.
BACKPLANE TEST DATA OUTPUT: This output drives test data from the
’PSC110F and the local TAPs, back toward the scan master controller.
11
9
2, 3, 4,
5, 6, 7
1
15,19,
24
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock
signal that controls all scan operations of the ’PSC110F and of the three (3)
local scan ports.
TEST RESET: An asynchronous reset signal (active low) which initializes the
’PSC110F logic.
SLOT IDENTIFICATION: The configuration of these six (6) pins is used to
identify (assign a unique address to) each ’PSC110F on the system backplane.
OUTPUT ENABLE for the Local Scan Ports, active low. When high, this
active-low control signal TRI-STATEs all three local scan ports on the
’PSC110F, to enable an alternate resource to access one or more of the three
(3) local scan chains.
TEST DATA OUTPUTS: Individual output for each of the three (3) local scan
ports.
18, 23,
27
16, 20,
25
17, 22,
26
TEST DATA INPUTS: Individual scan data input for each of the three (3) local
scan ports.
TEST MODE SELECT OUTPUTS: Individual output for each of the three (3)
local scan ports. TMSL does not provide a pull-up resistor (which is assumed
to be present on a connected TMS input, per the IEEE 1149.1 requirement)
LOCAL TEST CLOCK OUTPUTS: Individual output for each of the three (3)
local scan ports. These are buffered versions of TCKB.
8, 28 Power supply pins, 5.0V ±10%.
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Номер в каталогеОписаниеПроизводители
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