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PDF AD9866 Data sheet ( Hoja de datos )
| Número de pieza | AD9866 | |
| Descripción | 12-Bit Broadband Modem Mixed Signal Front End | |
| Fabricantes | Analog Devices | |
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Data Sheet
Broadband Modem Mixed-Signal Front End
AD9866
FEATURES
Low cost 3.3 V CMOS MxFE for broadband modems
12-bit DAC
2×/4× interpolation filter
200 MSPS DAC update rate
Integrated 23 dBm line driver with 19.5 dB gain control
12-bit, 80 MSPS ADC
−12 dB to +48 dB low noise RxPGA (<2.5 nV/√Hz)
Third order, programmable low-pass filter
Flexible digital data path interface
Half- and full-duplex operation
Backward-compatible with AD9975 and AD9876
Various power-down/reduction modes
Internal clock multiplier (PLL)
2 auxiliary programmable clock outputs
Available in 64-lead chip scale package or bare die
APPLICATIONS
Powerline networking
VDSL and HPNA
FUNCTIONAL BLOCK DIAGRAM
PWR DWN
MODE
TXEN/SYNC
TXCLK
ADIO[11:6]/
Tx[5:0]
ADIO[5:0]/
Rx[5:0]
RXE/SYNC
RXCLK
AGC[5:0]
SPI
AD9866
12
2-4X
TxDAC
IAMP
0 TO –7.5dB
0 TO –12dB
CLK
SYN.
2M CLK
MULTIPLIER
12
ADC
80MSPS
2-POLE
LPF
1-POLE
LPF
6
4 REGISTER
CONTROL
0 TO 6dB – 6 TO 18dB –6 TO 24dB
∆ = 1dB ∆ = 6dB
∆ = 6dB
IOUT_G+
IOUT_N+
IOUT_N–
IOUT_G–
CLKOUT_1
CLKOUT_2
OSCIN
XTAL
RX+
RX–
Figure 1.
GENERAL DESCRIPTION
The AD9866 is a mixed-signal front end (MxFE®) IC for
transceiver applications requiring Tx and Rx path functionality
with data rates up to 80 MSPS. Its flexible digital interface, power
saving modes, and high Tx-to-Rx isolation make it well-suited
for half- and full-duplex applications. The digital interface is
extremely flexible allowing simple interfaces to digital back
ends that support half- or full-duplex data transfers, thus often
allowing the AD9866 to replace discrete ADC and DAC
solutions. Power saving modes include the ability to reduce
power consumption of individual functional blocks or to power
down unused blocks in half-duplex applications. A serial port
interface (SPI®) allows software programming of the various
functional blocks. An on-chip PLL clock multiplier and
synthesizer provide all the required internal clocks, as well as
two external clocks from a single crystal or clock source.
The Tx signal path consists of a bypassable 2×/4× low-pass
interpolation filter, a 12-bit TxDAC, and a line driver. The
transmit path signal bandwidth can be as high as 34 MHz at an
input data rate of 80 MSPS. The TxDAC provides differential
current outputs that can be steered directly to an external load
or to an internal low distortion current amplifier. The current
amplifier (IAMP) can be configured as a current- or voltage-
mode line driver (with two external npn transistors) capable of
delivering in excess of 23 dBm peak signal power. Tx power can
be digitally controlled over a 19.5 dB range in 0.5 dB steps.
The receive path consists of a programmable amplifier
(RxPGA), a tunable low pass filter (LPF), and a 12-bit ADC.
The low noise RxPGA has a programmable gain range of
−12 dB to +48 dB in 1 dB steps. Its input referred noise is less
than 3.3 nV/√Hz for gain settings beyond 30 dB. The receive
path LPF cutoff frequency can be set over a 15 MHz to 35 MHz
range or simply bypassed. The 12-bit ADC achieves excellent
dynamic performance over a 5 MSPS to 80 MSPS span. Both
the RxPGA and the ADC offer scalable power consumption
allowing power/performance optimization.
The AD9866 provides a highly integrated solution for many
broadband modems. It is available in a space saving, 64-lead
lead frame chip scale package (LFCSP), and is specified over the
commercial (−40°C to +85°C) temperature range.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9866
Data Sheet
Parameter
PLL CLK MULTIPLIER
OSCIN Frequency Range
Internal VCO Frequency Range
Duty Cycle
OSCIN Impedance
CLKOUT1 Jitter5
CLKOUT2 Jitter6
CLKOUT1 and CLKOUT2 Duty Cycle7
Temp Test Level Min
Full IV
Full IV
Full II
25°C V
25°C III
25°C III
Full III
5
20
40
45
Typ Max Unit
100//3
12
6
80
200
60
55
MHz
MHz
%
ΜΩ//pF
ps rms
ps rms
%
1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).
2 TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, FOUT = 5 MHz, 4× interpolation.
3 IOUN full-scale current = 80 mA, fOSCIN= 80 MHz, fDAC=160 MHz, 2× interpolation.
4 Use external amplifier to drive additional load.
5 Internal VCO operates at 200 MHz , set to divide-by-1.
6 Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN.
7 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.
Rx PATH SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; half- or full-duplex operation with CONFIG = 0 default power bias
settings, unless otherwise noted.
Table 2.
Parameter
Rx INPUT CHARACTERISTICS
Input Voltage Span (RxPGA gain = −10 dB)
Input Voltage Span (RxPGA gain = +48 dB)
Input Common-Mode Voltage
Differential Input Impedance
Temp Test Level
Full III
Full III
25°C III
25°C III
Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB)
Input Voltage Noise Density (RxPGA Gain = 36 dB, f−3 dBF = 26 MHz)
Input Voltage Noise Density (RxPGA Gain = 48 dB, f−3 dBF = 26 MHz)
RxPGA CHARACTERISTICS
Minimum Gain
Maximum Gain
Gain Step Size
Gain Step Accuracy
Gain Range Error
RxLPF CHARACTERISTICS
Cutoff Frequency (f−3 dBF ) range
Attenuation at 55.2 MHz with f−3 dBF = 21 MHz
Pass-Band Ripple
Settling Time to 5 dB RxPGA Gain Step @ fADC = 50 MSPS
Settling Time to 60 dB RxPGA Gain Step @ fADC = 50 MSPS
ADC DC CHARACTERISTICS
Resolution
Conversion Rate
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
NA
FULL
III
III
III
III
III
III
III
III
III
III
III
III
III
NA
II
Min Typ
Max Unit
6.33 V p-p
8 mV p-p
1.3 V
400 Ω
4.0 pF
53 MHz
2.7 nV/√Hz
2.4 nV/√Hz
−12
48
1
Monotonic
0.5
dB
dB
dB
dB
dB
15
20
±1
20
100
35 MHz
dB
dB
ns
ns
12
5
Bits
80 MSPS
Rev. C | Page 4 of 47
5 Page 
AD9866
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ADIO11/Tx[5] 1
ADIO10/Tx[4] 2
ADIO9/Tx[3] 3
ADIO8/Tx[2] 4
ADIO7/Tx[1] 5
ADIO6/Tx[0] 6
ADIO5/Rx[5] 7
ADIO4/Rx[4] 8
ADIO3/Rx[3] 9
ADIO2/Rx[2] 10
ADIO1/Rx[1] 11
ADIO0/Rx[0] 12
RXEN/RXSYNC 13
TXEN/TXSYNC 14
TXCLK/TXQUIET 15
RXCLK 16
PIN 1
IDENTIFIER
AD9866
TOP VIEW
(Not to Scale)
48 AVSS
47 AVSS
46 IOUT_N–
45 IOUT_G–
44 AVSS
43 AVDD
42 REFIO
41 REFADJ
40 AVDD
39 AVSS
38 RX+
37 RX–
36 AVSS
35 AVDD
34 AVSS
33 REFT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED TO GND.
Figure 2. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
1 ADIO11
Tx[5]
2 to 5
ADIO10 to 7
Tx[4 to 1]
6 ADIO6
Tx[0]
7 ADIO5
Rx[5]
8, 9 ADIO4, 3
Rx[4, 3]
10 ADIO2
Rx[2]
11 ADIO1
Rx[1]
12 ADIO0
Rx[0]
13 RXEN
RXSYNC
14 TXEN
TXSYNC
Mode1
Description
HD MSB of ADIO Buffer
FD MSB of Tx Nibble Input
HD Bits 10 to 7 of ADIO Buffer
FD Bits 4 to 1 of Tx Nibble Input
HD Bit 6 of ADIO Buffer
FD LSB of Tx Nibble Input
HD Bit 5 of ADIO Buffer
FD MSB of Rx Nibble Output
HD Bits 4 to 3 of ADIO Buffer
FD Bits 4 to 3 of Rx Nibble Output
HD Bit 2 of ADIO Buffer
FD Bit 2 of Rx Nibble Output
HD Bit 1 of ADIO Buffer
FD Bit 1 of Rx Nibble Output
HD LSB of ADIO Buffer
FD LSB of Rx Nibble Output
HD ADIO Buffer Control Input
FD Rx Data Synchronization Output
HD Tx Path Enable Input
FD Tx Data Synchronization Input
Rev. C | Page 10 of 47
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9866.PDF ] | |
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