PDF MT93L04 Data sheet ( Hoja de datos )

Número de pieza	MT93L04
Descripción	128-Channel Voice Echo Canceller
Fabricantes	Zarlink Semiconductor
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No Preview Available ! www.DataSheet4U.com MT93L04 128-Channel Voice Echo Canceller Data Sheet Features • MT93L04 is a Multi-chip Module (MCM) consisting of 4 MT93L00 devices thus providing 128 channels of 64 msec Echo Cancellation • Each device (MT93L00) is independent of the each other • Each device has the capability of cancelling echo over 32 channels • The MCM module provides more than 40% board space savings • Each device (MT93L00) can be programmed independently in any mode e.g back to back or extended delay to provide capability of cancelling different echo tails • Each device has the same Jtag identification code Applications • Voice over IP network gateways • Voice over ATM, Frame Relay • T1/E1/J1 multichannel echo cancellation • Wireless base stations January 2006 Ordering Information MT93L04AG 365 Ball BGA Trays MT93L04AG2 365 Ball BGA Trays Pb Free Tin/Silver/Copper -40°C to +85°C • Echo Canceller pools • DCME, satellite and multiplexer systems Description The MT93L04 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The MT93L04 architecture contains 64 groups of two echo cancellers (ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation. This provides 128 channels of 64 milliseconds to 64 channels of 128 milliseconds echo cancellation or any combination of the two configurations. The MT93L04 supports ITU-T G.165 and G.164 tone disable requirements. MT93L00 1 MT93L00 2 MT93L00 4 MT93L00 3 Figure 1 - MT93L04 is MULTI-CHIP Module Consisting of 4 MT93L00 Devices 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001-2006, Zarlink Semiconductor Inc. All Rights Reserved. 1 page Pin Description (continued) Signal Name Signal Type IRQB_d1 User Signal DSB_d1 CSB_d1 R/WB_d1 DTAB_d1 User Signal User Signal User Signal User Signal D(0)_d1 D(1)_d1 D(2)_d1 D(3)_d1 D(4)_d1 D(5)_d1 D(6)_d1 D(7)_d1 A(0)_d1 A(1)_d1 A(2)_d1 A(3)_d1 A(4)_d1 A(5)_d1 A(6)_d1 A(7)_d1 A(8)_d1 A(9)_d1 A(10)_d1 User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal User Signal MT93L04 Data Sheet BGA Ball # J5 H2 K3 H3 K4 H4 K5 H5 G4 G5 F4 F5 E5 D4 E6 D5 E7 D7 E8 E10 D8 D10 C10 B10 Signal Description Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. Address A0 to A10 (Input). These inputs provide the A10 - A0 address lines to the internal registers. 5 Zarlink Semiconductor Inc. 5 Page Pin Description (continued) Signal Name Signal Type Sout_d2 Signal Rout_d2 Signal Sin_d2 Signal Rin_d2 Signal FOIb_d2 Signal C4IB_d2 Signal SC_set_d2 ICO SM_mclk_d2 ICO ST_mclk_d2 ICO SC_en_d2 ICO SC_In_d2 ICO SC_Reset:_d2 ICO SC_Fclk_d2 ICO Tsig(8)_d2 NC Tsig(9)_d2 NC Tsig(10)_d2 NC MT93L04 Data Sheet BGA Ball # L1 N4 L2 N3 N2 L3 N1 L4 M5 L5 M1 M2 M3 M4 P1 P2 Signal Description Send PCM Signal Output (Output). Port 1 TDM data output streams.Sout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Output (Output). Port 2 TDM data output streams. Rout pin outputs serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Send PCM Signal Input (Input). Port 2 TDM data input streams. Sin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Receive PCM Signal Input (Input). Port 1 TDM data input streams.Rin pin receives serial TDM data streams at 2.048 Mb/s with 32 channels per stream. Frame Pulse (Input). This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS or GCI interface specifications. Serial Clock (Input). 4.096 MHz serial clock for shifting data in/out on the serial streams (Rin, Sin, Rout, Sout). Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation Internal Connection. Connected to VSS for normal operation No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. No connection. The pin must be left open for normal operation. 11 Zarlink Semiconductor Inc. 11 Page

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