PDF MT91L61 Data sheet ( Hoja de datos )

Número de pieza	MT91L61
Descripción	(MT91L60 / MT91L61) ISO2-CMOS 3 Volt Multi-Featured Codec
Fabricantes	MITEL
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No Preview Available ! www.DataSheet4U.com ISO2-CMOS MT91L60/61 3 Volt Multi-Featured Codec (MFC) Advance Information Features • Single 2.7-3.6 volt supply operation • MT91L61 version features a delayed framing pulse in SSI and ST-BUS modes to facilitate cascaded devices • Programmable µ-Law/A-Law Codec and Filters • Programmable ITU-T (G.711)/sign-magnitude coding • Programmable transmit, receive and side-tone gains • Fully differential interface to handset transducers - including 300 ohm receiver driver • Flexible digital interface including ST-BUS/SSI • Serial microport • Low power operation • ITU-T G.714 compliant • Multiple power down modes Applications • Battery operated equipment • Digital telephone sets • Cellular radio sets • Local area communications stations • Pair Gain Systems • Line cards DS5224 ISSUE 3 August 1999 Ordering Information MT91L61AE MT91L60AE MT91L61AS MT91L60AS MT91L61AN MT91L60AN 24 Pin Plastic DIP (600 mil) 24 Pin Plastic DIP (600 mil) 24 Pin SOIC 20 Pin SOIC 24 Pin SSOP 20 Pin SSOP -40°C to +85°C Description The MT91L60/61 3V Multi-featured Codec incorporates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip anti-alias ﬁlters, reference voltage and bias source. The device supports both ITU-T and sign- magnitude A-Law and µ-Law requirements. The MT91L60/61 is a true 3V device employing a fully differential architecture to ensure wide dynamic range. Complete telephony interfaces are provided for connection to handset transducers. Internal register access is provided through a serial microport compatible with various industry standard micro-controllers. The MT91L60/61 is fabricated in Mitel's ISO2-CMOS technology ensuring low power consumption and high reliability. VSSD VDD VSSA VBias VRef Din Dout STB/F0i CLOCKin STBd/FOod (MT91L61only) FILTER/CODEC GAIN ENCODER 7dB DECODER -7dB Transducer Interface Flexible Digital Interface Timing ST-BUS C&D Channels Serial Microport PWRST IC CS DATA1 DATA2 SCLK Figure 1 - Functional Block Diagram M- M+ HSPKR + HSPKR - A/µ/IRQ 1 1 page Advance Information MT91L60/61 National Semiconductor Microwire speciﬁcations provides access to all MT91L60/61 internal read and write registers. This microport consists of a transmit/ receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a synchronous data clock pin (SCLK). For D-channel contention control, in ST-BUS mode, this interface provides an open-drain interrupt output (IRQ). The microport dynamically senses the state of the serial clock (SCLK) each time chip select becomes active. The device then automatically adjusts its internal timing and pin conﬁguration to conform to Intel or Motorola/National requirements. If SCLK is high during chip select activation then Intel mode 0 timing is assumed. The DATA1 pin is deﬁned as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during chip select activation then Motorola/National timing is assumed. Motorola processor mode CPOL=0, CPHA=0 must be used. DATA1 is deﬁned as the data transmit pin while DATA2 becomes the data receive pin. Although the dual port Motorola controller conﬁguration usually supports full-duplex communication, only half-duplex communication is possible in the MT91L60/61. The micro must discard non-valid data which it clocks in during a valid write transfer to the MT91L60/61. During a valid read transfer from the MT91L60/61 data simultaneously clocked out by the micro is ignored by the MT91L60/ 61. All data transfers through the microport are two-byte transfers requiring the transmission of a Command/ Address byte followed by the data byte written or read from the addressed register. CS must remain asserted for the duration of this two-byte transfer. As shown in Figures 5 and 6 the falling edge of CS indicates to the MT91L60/61 that a microport transfer is about to begin. The ﬁrst 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the MT91L60/61 and the microcontroller. At the end of the two-byte transfer CS is brought high again to terminate the session. The rising edge of CS will tri-state the output driver of DATA1 which will remain tri-stated as long as CS is high. Intel processors utilize least signiﬁcant bit ﬁrst transmission while Motorola/National processors employ most signiﬁcant bit ﬁrst transmission. The MT91L60/61 microport automatically accommodates these two schemes for normal data bytes. However, to ensure decoding of the R/W and Serial Port PCM Din Decoder Filter/Codec and Transducer Interface Default Bypass Receive Filter Gain 0 to -7 dB (1 dB steps) -6 dB -6.0 dB or 0 dB Receiver Driver Side-tone -9.96 to +9. 96 dB (3.32 dB steps) HSPKR + 75Ω HSPKR - 75Ω Handset Receiver (150Ω) -11 dB PCM Dout Encoder Transmit Filter GGaaiinn 0(10todtoB++7s7teddpBBs) Transmit Gain -0.37 dB or 8.93 dB Transmit Gain 6.37 dB Internal To Device Figure 3 - Audio Gain Partitioning M+ Transmitter M- Microphone External To Device 5 5 Page Advance Information Applications Figure 8 shows an application in a wireless phone set. Figure 9 shows an MT9161B’s delayed frame pulse driving a second MT9161B. This conﬁguration would be used where multiple CODEC’s were using a data bus (an example being Mitel’s ST-BUS). MT91L60/61 00 RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1 TxFG0 Gain Control Register 1 01 - - - - - STG2 STG1 STG0 Gain Control Register 2 02 - - - - - - - DrGain Path Control 03 PDFDI PDDR RST 04 CEN DEN D8 - TxMute RxMute TxBsel RxBsel Control Register 1 A/µ Smag/ CSL2 CSL1 CSL0 Control Register 2 ITU-T 05 C7 C6 C5 C4 C3 C2 C1 C0 C-Channel Register 06 D7 D6 D5 D4 D3 D2 D1 D0 D-Channel Register 07 - - - - PCM/ loopen - - ANALOG Table 2: 3V Multi-featured Codec Register Map Loop Back Note: Bits marked "-" are reserved bits and should be written with logic "0" 11 11 Page

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