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PDF AH103A Data sheet ( Hoja de datos )
| Número de pieza | AH103A | |
| Descripción | Amplifier | |
| Fabricantes | WJ Communication | |
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AH103A
High Gain, High Linearity ½-Watt Amplifier
The Communications Edge TM
Product Information
Product Features
Product Description
Functional Diagram
• 60 – 2700 MHz
• +27 dBm P1dB
• +46 dBm Output IP3
• 29 dB Gain @ 900 MHz
• Excellent ACPR
• MTTF > 100 Years
The AH103A is a high gain, high linearity ½-Watt
amplifier. This device is comprised of two individual
MMIC amplifiers internally and can be used with an
external interstage match for any of the mobile
infrastructure frequency bands. The dual-stage
amplifier achieves up to +46 dBm IP3 performance
with 29 dB gain.
• Lead-free/green/RoHS-compliant The device conforms to WJ Communications’ long
SOIC-8 Package w/ heat slug history of producing high reliability and quality
components. The AH103A has an associated MTTF
Applications
• Mobile Infrastructure
• W-LAN / ISM / RFID
of a minimum of 100 years at a mounting
temperature of 85 °C and is housed in a lead-free
/green/RoHS-compliant SOIC-8 package. All
devices are 100% RF & DC tested.
• MDS / MMDS Infrastructure
The product is targeted for use as driver amplifiers
for wireless infrastructure where high performance
and high linearity are required.
1
2
3 AMP 1
4
AMP 2
8
7
6
5
Function
Amp2 in
Amp1 out / Bias 1
Ground
RF in (Amp1 in)
RF out (Amp2 out)
Bias 2
Pin No.
1
2
3, 5, 8,
Backside copper
4
6
7
Specifications (1)
Typical Performance (1)
Parameter
Operational Bandwidth
Test Frequency
Gain
Output IP3
Output P1dB
Test Frequency
Gain
Input Return Loss
Output Return Loss
Output IP3 (2)
Output P1dB
Noise Figure
Supply Voltage (Amp1)
Supply Voltage (Amp2)
Operating Current (3)
Units
MHz
MHz
dB
dB
dBm
MHz
dB
dB
dB
dBm
dBm
dB
V
V
mA
Min
60
23.5
+42
+25
225
Typ
900
29.1
+46
+27
1900
25.4
19
11
+45
+26.7
3
+4.5
+9
275
Max
2700
330
1. Test conditions unless otherwise noted: 25 ºC, Vdd1 = +4.5 V, Vdd2 = +9 V, in a tuned application circuit.
2. 3OIP measured with two tones at an output power of +8 dBm/tone separated by 10 MHz. The
suppression on the largest IM3 product is used to calculate the 3OIP using a 2:1 rule.
3. Amp1 and Amp2 have a typical current draw of 75 and 200 mA, respectively.
Parameter
Frequency
Gain
Input Return Loss
Output Return Loss
Output IP3
Output P1dB
IS-95 Ch. Power (4)
@ -45 dBc ACPR
W-CDMA Ch. Power (5)
@ -45 dBc ACPR / ACLR
Noise Figure
Supply Bias Amp1
Supply Bias Amp2
Units
MHz
dB
dB
dB
dBm
dBm
dBm
dBm
dB
Typical
900 1900 2140
29.1 25.4
25
20 19 24
19 11 11
+46 +45 +45
+27 +26.7 +26.3
+20.7 +20.5
+18.5
2.5 3 2.9
+4.5 V @ 75 mA
+9 V @ 200 mA
4. ACPR is measured at 900 and 1900 MHz with a IS-95, 9 Channels Forward, ±885 kHz offset, 30
kHz BW, 1.23 MHz Channel BW.
5. ACLR is measured at 2140 MHz with a 3GPP W-CDMA, Test Model 1+64 DPCH, ±5 MHz
offset, 3.84 MHz Channel BW.
Absolute Maximum Rating
Parameter
Operating Case Temperature
Storage Temperature
DC Voltage (pin 2)
DC Voltage (pin 6, 7)
RF Input Power (continuous)
Junction Temperature
Rating
-40 to +85 °C
-55 to +125 °C
+6 V
+11 V
4 dB above Input P1dB
+220 °C
Ordering Information
Part No.
AH103A-G
AH103A-PCB900
AH103A-PCB1900
AH103A-PCB2140
Description
High Gain ½-Watt Amplifier
(lead-free/green/RoHS-compliant SOIC-8 Pkg)
0.7 – 1.0 GHz Evaluation Circuit
1.8 – 2.0 GHz Evaluation Circuit
2.1 – 2.2 GHz Evaluation Circuit
Operation of this device above any of these parameters may cause permanent damage.
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
Page 1 of 6 March 2005
1 page  
AH103A
High Gain, High Linearity ½-Watt Amplifier
The Communications Edge TM
Product Information
Application Circuit: 2110 – 2170 MHz (AH103AG-PCB2140)
Typical RF Performance at 25°C
Frequency
2140 MHz
Gain 25 dB
Input Return Loss
24 dB
Output Return Loss
11 dB
Output IP3
+45 dBm
Output P1dB
+26.3 dBm
W-CDMA Ch. Power
@ -45 dBc ACPR
+18.5 dBm
Noise Figure
2.9 dB
Supply Voltage
+9 V
Supply Current
275 mA
Notes:
1. A voltage regulator is used in this circuit (U2) to drop the +9 V to a +5 V usable supply for the first internal amplifier. It is permissible to remove the
regulator and operate the 1st amplifier stage directly off of +5 V supply onto Test Point 1 (TP1). The use of a +5 V supply on the 1st amplifier stage
requires a dropping resistor of 6.8 Ω. A +4.5 V supply can also be used to bypass the 6.8 Ω and can be applied to Test Point 2 (TP2).
S-Parameters
27 0
S21 S11 S22
26 -5
25 -10
24 -15
23 -20
22
2050
2100 2150 2200
Frequency (MHz)
-25
2250
30
20
10
0
-10
-20
-30
0
Wideband S-Parameters
S21 S11 S22
500 1000 1500 2000 2500 3000
Frequency (MHz)
Noise Figure
5
Output IP3
48
ACLR vs. Channel Power
3GPP W-CDMA, Test Model 1+64 DPCH, ±5 MHz offset, 2140 MHz
-40
4 46
-45
3 44
2 42 -50
1 40 -55
0 38
2000 2050 2100 2150 2200
6
Frequency (MHz)
-60
8 10 12 14 16
14 15 16 17 18 19
Output Power per tone (dBm)
Output Channel Power (dBm)
Specifications and information are subject to change without notice
WJ Communications, Inc • Phone 1-800-WJ1-4401 • FAX: 408-577-6621 • e-mail: [email protected] • Web site: www.wj.com
Page 5 of 6 March 2005
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet AH103A.PDF ] | |
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