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PDF MDS105 Data sheet ( Hoja de datos )
| Número de pieza | MDS105 | |
| Descripción | Unmanaged 5-Port 10/100 Mbps Ethernet Switch | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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MDS105
Unmanaged 5-Port 10/100 Mbps
Ethernet Switch
Data Sheet
Features
November 2003
• 4 10/100 Mbps auto-negotiating RMII ports
Ordering Information
• 1 10/100 Mbps auto-negotiating MII/serial port
(Port 4) that can be used as a WAN uplink or as a
5th port
MDS105AL 208 Pin PQFP
• External I2C EEPROM for power-up configuration
-40°C to +85°C
- Default mode allows operation without external
EEPROM
• Up to 4 port-based VLANs
• Full wire-speed layer 2 switching on all ports (up
to 1.448 M packets per second)
• Provides port-based prioritization of packets on up
to 2 ports (0-1)
- Input ports are defined to be high or low priority
- Allows explicit identification of IP Phone ports
• Internal 1 k MAC address table
• Ports 0 & 1 can be trunked to provide a 200 Mbps
- Auto address learning
link to another switch or server
- Auto address aging
• Utilizes a single low-cost external Pipelined,
SyncBurst SRAM (SBRAM) for buffer memory
• Leading edge QoS capabilities provided based on
802.1p and IP TOS/DS field
- 256 k bytes or 512 k bytes (1 chip)
- 2 queues per output port
• Flow Control capabilities
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- Packet scheduling based on Weighted Round-
- Provides back pressure for half duplex
Robin (WRR) and Weighted Random EaDrlyataSheet4U.c- om802.3x flow control for full duplex
Detection/Drop (WRED)
• Special power-saving mode for inactive ports
- Without flow control can drop packets during
congestion using WRED
• Ability to support WinSock2.0 and Windows2000
smart applications
- 2 levels of packet drop provided
• Transmit delay control capabilities
• Supports both Full/Half duplex ports
- Provides maximum delay guarantee (<1 ms)
• Supports external parallel port for configuration
updates
• Port 3 can be used to mirror traffic from the other
3 ports (0-2)
- Supports mixed voice-data networks
• Optimized pin-out for easy board layout
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S MDS105
S 5-Port
R Switch
A Chip
M
RMII
Quad
10/100
Phy
MII
10/100
Phy
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of ZarDlinak tSaeSmhiceonedtu4cUtor.cInoc.m
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
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107 M8_TXCLK/S8_TXCLK
108 VDD
109 M8_TXEN[0]/S8_TXEN
110 M8_TXD[0]/S8_TXD
111 M8_TXD[1]
112 M8_TXD[2]
113 M8_TXD[3]
114 M8_LINK/S8_LINK
115 M8_DUPLEX/S8_DUPL
EX
116 M8_SPEED
117 VSS
118 M8_REFCLK
119 VDD
120 M_MDC
121 VSS
et4U.com
122 M_MDIO
123 SCL
124 SDA
125 TEST#
126 TRUNK_ENABLE
127 STROBE
128 DATA0
129 ACK
130 VDD (CORE)
131 TSTOUT[0]
132 TSTOUT[1]
133 TSTOUT[2]
134 TSTOUT[3]
135 TSTOUT[4]
136 TSTOUT[5]
137 TSTOUT[6]
138 TSTOUT[7]
139 T_MODE
140 VSS (CORE)
141 RSTOUT#
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MDS105
142 RSTIN#
143 MIRROR_CONTROL[0]
144 MIRROR_CONTROL[1]
145 MIRROR_CONTROL[2]
146 MIRROR_CONTROL[3]
147 VDD
148 SCLK
149 VSS
150 L_A[2]
151 L_A[17]
152 VDD
153 L_CLK
154 VSS
155 L_WE#
156 L_OE#
157 L_ADSC#
158 L_A[16]
159 VDD (CORE)
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160 L_A[15]
161 L_D[0]
162 VSS
163 L_D[1]
164 L_D[2]
165 L_D[3]
166 VDD
167 L_D[4]
168 L_D[5]
169 L_D[6]
170 L_D[7]
171 VSS (CORE)
172 L_D[8]
173 L_D[9]
174 L_D[10]
175 VDD
176 L_D[11]
177 L_D[12]
Data Sheet
178 L_D[13]
179 L_D[14]
180 VSS
181 L_D[15]
182 L_D[16]
183 L_D[17]
184 VDD (CORE)
185 L_D[18]
186 L_D[19]
187 L_D[20]
188 L_D[21]
189 VSS
190 L_D[22]
191 L_D[23]
192 L_D[24]
193 L_D[25]
194 VDD
195 L_D[26]
196 L_D[27]
197 L_D[28]
198 VSS (CORE)
199 L_D[29]
200 L_D[30]
201 L_D[31]
202 VDD
203 L_A[18]
204 L_A[3]
205 L_A[4]
206 L_A[5]
207 VSS
208 L_A[6]
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MDS105
Data Sheet
4.0 Buffer Management
The MDS105 stores each input packet into the external frame buffer memory while determining the destination the
packet is to be forwarded to. The total number of packets that can be stored in the frame buffer memory depends
upon the size of the external SBRAM that is utilized. For a 256 KB SBRAM the MDS105 can buffer 170 packets.
For a 512 KB SBRAM the MDS105 can buffer 340 packets.
In order to provide good quality of service characteristics, the MDS105 must carefully allocate the available buffer
space. Such careful allocation can be accomplished using the external EEPROM to load the appropriate values into
the MDS105 configuration registers. The Low-Drop Precedence Buffer Threshold (LPBT) register assures that
traffic designated as low-drop actually receives reserved buffer space. The designer can set the minimum number
of buffers reserved for low-drop unicast traffic, by setting this register with a value between 0 and 255. Unreserved
buffers are treated as shared, and are accessible to all types of incoming traffic.
To set the maximum number of buffers permitted for all multicast packets, use the Multicast Buffer Control Register
(MBCR). Unlike the LPBT register, the MBCR register does not define a reserved area of buffer memory, but
instead provides a bound on the number of multicast packets that can be buffered at any one time.
During operation the MDS105 will continuously monitor the amount of frame buffer memory that is available, and
when the unused buffer space falls below a designer configurable threshold, the MDS105 will initiate flow control if
enabled or WRED if not. This threshold is set using the FCB Buffer Low Threshold (FCBST) register.
5.0 Virtual LANs
The MDS105 provides the designer the ability to define a single port-based Virtual LAN (VLAN) for each of the five
ports. This VLAN is individually defined for each port using the Port Control Registers (ECR1Px[6:4]). Bits [6:4]
et4U.com allow the designer to define a VLAN ID (value between 0 – 3) for each port.
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When packets arrive at an input of the MDS10D5a, ttaheShseeaertc4hUe.cnogmine will determine the VLAN ID for that port, and
then determine which of the other ports are also members of that VLAN by matching their assigned VLAN ID
values. The packet will then be transmitted to each port with the same VLAN ID as the source port.
6.0 Port Trunking
Port trunking allows the designer to configure the MDS105, such that ports 0 and 1 are defined as a single logical
port. This provides a 200 Mbps link to a switch or server utilizing two 100 Mbps ports in parallel.
Ports 0 and 1 can be trunked by pulling the TRUNK_EN pin to the high state. In this mode, the source MAC
addresses of all packets received from the trunk are checked against the MCT database to ensure that they have a
port ID of 0 or 1. Packets that have a port ID other than 0 and 1 will cause the MDS105 to learn the new MAC
address for this port change.
On transmission, the trunk port is determined by hashing the source and destination MAC addresses. This provides
a mapping between each MAC address and an associated trunk port. Subsequent packets with the same MAC
address will always utilize the same trunk port.
The MDS105 also provides a safe fail-over mode for port trunking. If one of the two ports goes down, as identified
by the port’s link status signal, then the MDS105 will switch all traffic over to the remaining port in the trunk. Thus,
the trunk link is maintained, albeit at a lower effective bandwidth.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MDS105.PDF ] | |
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