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PDF STEL5269+512 Data sheet ( Hoja de datos )
| Número de pieza | STEL5269+512 | |
| Descripción | Convolutional Encoder Viterbi Decoder | |
| Fabricantes | Intel | |
| Logotipo |  |
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STEL-5269+512
Data Sheet
STEL-5269+512
Convolutional Encoder
Viterbi Decoder
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1 page  
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ENLATCH
This is the encoder Output Latch Enable. The new
symbol is clocked into the output latch and appears on
the OSYMB pin on the rising edge of ENLATCH.
When MODE is low the symbol selected will depend
on the states of the SEL A and SEL B lines, which
should be stable on the rising edge of ENLATCH.
When MODE is high the symbol selection is internal,
and the frequency of the ENLATCH signal should be
2 or 3 times the frequency of the DATACLK, depending
on the rate selected.
ICLK, OCLK
System Clock. A crystal may be connected between
ICLK and OCLK or a CMOS level clock may be fed
into ICLK only. The clock frequency should be at least
70 times the data rate but no more than 36 MHz.
DRATE
The Decoder Rate input selects whether the decoder
will read two symbols (DRATE set high) or three
symbols (DRATE set low)) for every data bit decoded.
During rate 1/2 operation the symbol G3 on inputs
G3D2-0 is completely ignored by the decoder.
G1D2-0, G2D2-0, G3D2-0
The three 3-bit soft decision symbols are connected to
these inputs and loaded into the input registers on the
falling edge of DRDY. The order in which the symbols
are entered into the decoder from the registers depends
on the state of the SYNC0 and SYNC1 inputs. The
decoder can make use of soft decision information,
which includes both polarity information and a
confidence measure, to improve the decoder
performance. If hard decision (single bit) symbols are
used the signals are connected to pins G1D2, G2D2 and
G3D2 and the other inputs are connected to VDD. See
SM2C for a description of the input data codes.
DRDY
The Data Ready signal is used to load symbols into the
decoder. This signal is edge triggered and a new set of
symbols is latched into the input registers on each
falling edge of the DRDY input.
SM2C
The state of the Signed Magnitude/2's Complement
input determines the format of the incoming soft-
decision symbols into the decoder. When SM2C is
high the input code is Signed Magnitude, and when it
is low the code is Two's Complement. The codes are
shown in the following table:
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CODE CONTROL:
SYMBOL INPUT:
Most Confident '+' level
Data = 0
Least Confident '+' level
Least Confident '–' level
Data = 1
Most Confident '–' level
SM2C = 1
GxD2-0
011
010
001
000
100
101
110
111
SM2C = 0
GxD2-0
011
010
001
000
111
110
101
100
When using hard decision data, SM2C should be set
high, the G12 and G22 input pins used for the symbol
signals and G11-0 and G21-0 tied high.
SYNC0, SYNC1
The Symbol Sync inputs are used for auto node sync
operation. When using the internal auto node sync
mode these two pins are connected to SST0 and SST1,
respectively. The operation of the decoder is affected
in the following way by the SYNC0 and SYNC1 inputs:
RATE SYNC0 SYNC1
10
11
10
11
00
01
00
01
0
0
1
1
0
0
1
1
Symbol entered into
decoder inputs during
symbol period N
G12-0 G22-0 G32-0
G1N
G2N
G2N–1 G1N
G2N
G1N
Invalid state
–
–
–
G1N
G2N
G3N–1 G1N
G2N–1 G3N-1
Invalid state
G3N
G2N
G1N
When RATE = 1 (rate 1/2 operation) only one possible
alternative state exists in any given situation. This
depends on whether the modulation format used was
BPSK (sequential symbols) or QPSK (parallel symbol
pairs). In this case the node sync process can be
improved by only using the SYNC input applicable for
the corresponding alternative sync state (i.e., SYNC0
for BPSK, SYNC1 for QPSK) and tying the other low to
prevent the node sync circuit from inadvertently
selecting the non-applicable state. When RATE = 0
(rate 1/3 operation) both alternative sync states
correspond to those possible with BPSK modulation.
5 STEL-5269+512
5 Page 
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APPLICATIONS INFORMATION
USING AUTOMATIC NODE SYNC
The automatic node sync circuit built into the STEL-
5269+512 can be used to provide node sync in
applications where this is not intrinsic to the nature
of the operation. The automatic node sync is enabled
by connecting the SST1 and SST0 outputs to the
SYNC1 and SYNC0 inputs, as shown below. The
threshold should be set according to the expected
signal to noise ratio of the input signal for optimum
operation of the system (see page 6). When
RATE = 1 (rate 1/2) only one possible alternative
state exists in any given situation. This depends on
whether the modulation format used was BPSK
(sequential symbols) or QPSK (parallel symbol pairs).
In this case the node sync process can be improved
by only using the SYNC input applicable for the
corresponding alternative sync state (i.e., SYNC0
3-bit Soft
Decision
Inputs
G1 DOUT
G2
G3 SYNC
STEL-5269
SYNC0 SST0
SYNC1 SST1
Data
Out
In/Out
of Sync
for BPSK, SYNC1 for QPSK) and tying the other low
to prevent the node sync circuit from inadvertently
selecting the non-applicable state. When RATE = 0
(rate 1/3) both alternative sync states correspond to
those possible with BPSK modulation. Note that
whenever the states of the SYNC0 and SYNC1
inputs are changed there will be a delay of 42 bit
periods before valid data starts appearing at DOUT.
DECODER OPERATION WITH BPSK
The Viterbi decoder is designed to operate with a
QPSK demodulator, which provides the G1 and G2
symbols as parallel pairs from the I and Q channels.
Operating the device with a BPSK demodulator,
which provides the G1 and G2 symbols as sequential
pairs, requires some external circuitry to convert the
sequential pairs into parallel pairs. The circuit shown
here assumes that the symbols are clocked out of the
demodulator on the rising edges of the clock signal.
The symbol rate clock is divided by 2 to generate a
bit rate clock. One phase of the clock is used to latch
alternate symbols into the upper 3-bit latch and the
opposite phase latches the interleaving symbols
into the lower 3-bit latch. The automatic node sync
circuit in the STEL-5269 will take care of the symbol
3-bit Soft
Decision
Input
D1 Q1
D2 Q2
D3 Q3
G1D 2
G1D 1
G1D 0
Data
Clock
DQ
Q
D1 Q1
D2 Q2
D3 Q3
G2D 2
G2D 1
G2D 0
DQ
Q
DRDY
(All latches are
74HC74/175 type)
ambiguity which occurs in this system. A third
clock phase provides the DRDY signal to the
STEL-5269. Again, the phase ambiguity will be
taken care of by the automatic node sync circuit.
ENCODER OPERATION
The encoder section requires a clock at twice the
data rate when operating at rate 1/2. A suitable
circuit is shown below. The input clock runs at twice
the data rate and is divided to produce the data
clock itself. The encoder produces serialized symbol
pairs suitable for BPSK modulation directly. The
optional circuit shown will convert these into parallel
pairs suitable for QPSK modulation.
Data In
Data
Clock
2X Data
Clock
DQ
Q
(All latches are 74HC74 type)
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STEL-5269
DATAIN
ENLATCH
DATACLK
OSYMB
BPSK Out
DQ
Q
DQ
Q
G1
(I)
DQ
Q
G2
(Q)
Optional circuit
for QPSK only
11 STEL-5269+512
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet STEL5269+512.PDF ] | |
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