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CXD1947Q PDF даташит

Спецификация CXD1947Q изготовлена ​​​​«Sony Corporation» и имеет функцию, называемую «IEEE1394 LINK Layer / PCI Bridge LSI».

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Номер произв CXD1947Q
Описание IEEE1394 LINK Layer / PCI Bridge LSI
Производители Sony Corporation
логотип Sony Corporation логотип 

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CXD1947Q Даташит, Описание, Даташиты
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PRELIMINARY
IEEE1394 LINK Layer / PCI Bridge LSI
CXD1947Q
Overview
The CXD1947Q is a single-chip implementation of the
link layer protocol of the 1394 Serial Bus, with additional
features to support the transaction and bus management
layers.
The CXD1947Q includes a PCI bus interface and mul-
tiple DMA engines to enable high performance bus
transfers.
Features
• 1394 Link Layer/PCI Bridge
• Conforms to IEEE1394 high speed Serial Bus
• Supports 100Mb/s and 200Mb/s 1394 bus speeds
• Conforms to PCI version 2.1 specification
• Supports 6 independent programmable DMA channels
— Asynchronous transmit (1)
— Asynchronous receive (1)
— Isochronous transmit (2)
— Isochronous receive (2)
• Three 128-word-deep FIFOs
— Asynchronous transmit
— Isochronous transmit
— Receive
160 pin QFP
• Includes interfaces to
— 1394 PHY interface (CXD1944 or equivalent)
— ROM (64K x 8)
— Silicon Serial ROM
• Supports big and little Endian data formats
Device Structure
Silicon gate CMOS IC
Recommended Operating Conditions
• Supply voltage
VDD 3.0 to 3.6
• Operating temperature range Topr –20 to +75
V
°C
Block Diagram
PCI BUS
PCI INF
MBIU
ITDMA
ATDMA
RDMA
IRDMA
ALIGN
ALIGN
ALIGN
ITF
ATF
RF
LINK
PHY
CORE
SSN INF
ROM INF
CNTL REG
MBIU: Master Bus Interface
ITDMA: Isochronous Transmit DMA
ATDMA: Asynchronous Transmit DMA
RDMA: Receive DMA
wIRwDMwA.:DIsaotcahSronhoeuseRt4eUce.ivceoDmMA
ALIGN:
ITF:
ATF:
RF:
SSN INF:
Data Aligner
Isochronous Transmit FIFO
Asynchronous Transmit FIFO
Receive FIFO
Silicon Serial Number
PHY:
ROM INF:
CNTL REG:
Link Layer/Physical Layer
1394 Interface
ROM Interface
Control Registers
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication
or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony
cannot assume responsibility for any problems arising out of the use of these circuits.
–1– 10/18/96









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Pin Configuration
VDD
PHYDATA3
PHYDATA2
PHYDATA1
PHYDATA0
PCTL1
VSS
VDD
LPSTAT
PCTL0
LREQ
DIRECT
SCLK
VSS
VDD
NC
RESET
PCICLK
PCIGNT
PCIREQ
VSS
VDD
NC
PCIAD31
PCIAD30
PCIAD29
PCIAD28
VSS
VDD
NC
PCIAD27
PCIAD26
PCIAD25
PCIAD24
VDD
VSS
NC
PCI_BE3
PCIIDSEL
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
160 PIN QFP
Preliminary CXD1947Q
80 VSS
79 ROMDT3
78 ROMDT2
77 VSS
76 VDD
75 NC
74 ROMDT1
73 ROMDT0
72 NC
71 NC
70 VSS
69 VDD
68 VST
67 TDO
66 TENA1
65 TDI
64 TCK
63 BCI
62 VSS
61 VDD
60 PCIAD0
59 PCIAD1
58 PCIAD2
57 PCIAD3
56 VSS
55 VDD
54 NC
53 INT
52 PCIAD4
51 PCIAD5
50 PCIAD6
49 PCIAD7
48 VSS
47 VDD
46 NC
45 PCIAD8
44 PCIAD9
43 PCIAD10
42 PCIAD11
41 VDD
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Preliminary CXD1947Q
Functions
1. Asynchronous Function
The CXD1947Q can transmit and receive all of the
defined 1394 packet formats. Packets to be transmitted
are read out of host memory and received packets are
written into host memory, both using DMA. CXD1947Q
can be programmed to act as a bus bridge between PCI
and 1394 by directly executing 1394 read and write
requests to the first 4GB of node offset address as read
and writes to PCI memory space. The CXD1947Q can
also be programmed to automatically place the data from
read response packets in the proper location in host
memory, then optionally interrupt the host processor to
indicate that the transaction is complete.
2. Isochronous Function
The CXD1947Q is capable of performing the cycle
master function as defined by 1394. This means it con-
tains a cycle timer and counter, and can transmit a spe-
cial packet called a “cycle start” after every rising edge of
the 8KHz cycle clock. The CXD1947Q can either gener-
ate the cycle clock from the 49.152MHz clock it receives
from the PHY, or use the “CycleIn” pin directly. When not
the cycle master, the CXD1947Q keeps its internal cycle
timer synchronized with the cycle master node by cor-
recting its own cycle timer with the reload value from the
cycle start packet. The CXD1947Q supports two isochro-
nous transmit channels and two isochronous receive
channels. The CXD1947Q can regulate the rate of trans-
mit to emulate data rates which are synchronous with,
but not even multiples of, the 8KHz cycle clock.
3. PCI Interface
This block acts both as a master and a slave on the
PCI bus. As a slave, it decodes and responds to access-
es to registers within CXD1947Q. As a master, it acts on
behalf of the DMA units to generate transactions on the
PCI bus. These transactions are used to move streams
of data between system memory and the devices, as
well as to read and write the DMA command lists.
4. DMA
The CXD1947Q supports six independent DMA chan-
nels: one Asynchronous Transmit channel, one
wAswynwch.DroanotauSs hReeceeti4veUc.chaonmnel, and four Isochronous
channels. The CXD1947Q also has Physical DMA capa-
bility to respond to incoming requests to physical
addresses. The DMA unit is made up of three controller
modules which support these various DMA functions.
Each module has access to the PCI Interface to perform
move operations, and is capable of sequencing through
buffer descriptor lists stored in main memory in order to
find the next buffer address after a channel exhausts the
previous buffer. This frees the system from stringent
interrupt response requirements after buffer completions.
Each DMA controller stores the current channel pro-
gram pointers and the current context for each of its
DMA channels. A 32-bit incrementer updates both the
Channel Program Pointers and the current buffer point-
ers. A 16-bit decrementer is used to adjust the count val-
ues for the channels. These incrementers and
decrementers will be shared if a Controller unit has multi-
ple channels.
5. Miscelleneous Functions
Upon detecting a bus reset, the CXD1947Q automati-
cally turns off the asynchronous transmitter. The receiver
remains on so that the CXD1947Q can receive PHY self-
ID packets during the self-ID process which immediately
follows the 1394 bus reset.
Following the bus reset operation, the CXD1947Q
receives the new node ID from the PHY and updates its
node ID register. Host system software must explicitly
restart the transmitter, presumably after it has corrected
the node addresses of any queued-up packets.
The CXD1947Q has an interface to a Dallas
Semiconductor Silicon Serial Number™ chip. This inter-
face retrieves a unique serial number which manage-
ment software then uses to uniquely identify the node for
which the CXD1947Q is attached on the 1394 interface.
6. Brief Hardware Description
The block diagram shows the CXD1947Q and its con-
nections in a host system. The CXD1947Q attaches to
the host via PCI bus. PCI provides an inexpensive and
moderatly high performance point for the connection of
I/O devices. PCI is a 32-bit, multiplexed address/data
bus, capable of performing 32-bit transfers at a rate of
33MHz.
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Номер в каталогеОписаниеПроизводители
CXD1947QIEEE1394 LINK Layer / PCI Bridge LSISony Corporation
Sony Corporation

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