PDF MT88L89 Data sheet ( Hoja de datos )

Número de pieza	MT88L89
Descripción	3V Integrated DTMFTransceiver with Adaptive Micro Interface
Fabricantes	Zarlink Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de MT88L89 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas
No Preview Available ! MT88L89 3V Integrated DTMF Transceiver with Adaptive Micro Interface Features DS5033 ISSUE 3 January 1999 Ordering Information • Complete DTMF transmitter/receiver MT88L89AE 20 Pin Plastic DIP • Low voltage operation (2.7-3.6V) • Pin for pin compatible with existing MT8880, MT8888 and MT8889 devices MT88L89AS 20 Pin SOIC MT88L89AN 24 Pin SSOP MT88L89AP 28 Pin PLCC -40°C to +85°C • Adaptive micro interface enables compatibility with Intel and Motorola processors • DTMF transmitter/receiver power-down via register control m• Adjustable guard time o• Automatic tone burst mode .c• Call progress tone detection to -30dBm UApplications t4• Credit card systems • Paging systems e• Repeater systems/mobile radio e• Interconnect dialers h• Pay phones ataS• Remote monitor/Control systems Description The MT88L89 is a monolithic DTMF transceiver with call progress ﬁlter. It is fabricated in CMOS technology offering low power consumption and high reliability. The receiver section is based upon the industry standard MT8870 DTMF receiver. The transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress ﬁlter can be selected allowing a microprocessor to analyze call progress tones. The MT88L89 utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT88L89 provides enhanced power-down features. The transmitter and receiver may independently be powered down via register control. w.DTONE ∑ D/A Converters ww .comIN+ UIN- et4GS heOSC1 ataSOSC2 Tone Burst Gating Cct. + Dial - Tone Filter Oscillator Circuit Bias Circuit Control Logic High Group Filter Low Group Filter Control Logic Row and Column Counters Digital Algorithm and Code Converter Steering Logic Transmit Data Register Status Register Control Register A Control Register B Receive Data Register www.DVDD VRef VSS ESt St/GT Figure 1 - Functional Block Diagram Data Bus Buffer Interrupt Logic I/O Control D0 D1 D2 D3 IRQ/CP DS/RD CS R/W/WR RS0 4-123 1 page MT88L89 VDD MT88L89 VDD St/GT ESt C1 Vc R1 tGTA = (R1C1) In (VDD / VTSt) tGTP = (R1C1) In [VDD / (VDD-VTSt)] Figure 5 - Basic Steering Circuit Guard Time Adjustment The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7): tREC ≥ tDPmax + tGTPmax - tDAmin t REC ≤ tDPmin + t GTPmin - tDAmax tID ≥ tDAmax + tGTAmax - tDPmin tDO ≤ tDAmin + tGTAmin - tDPmax Pin Description Pin # 20 24 28 8,9 3,5, 16, 10- 17 11 16 23- 25 Name NC No Connection. The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most tGTP = (RPC1) In [VDD / (VDD-VTSt)] tGTA = (R1C1) In (VDD/VTSt) VDD RP = (R1R2) / (R1 + R2) C1 St/GT R1 ESt VDD St/GT R2 a) decreasing tGTP; (tGTP < tGTA) tGTP = (R1C1) In [VDD / (VDD-VTSt)] tGTA = (RpC1) In (VDD/VTSt) RP = (R1R2) / (R1 + R2) C1 R1 ESt R2 b) decreasing tGTA; (tGTP > tGTA) Figure 6 - Guard Time Adjustment Description 4-127 5 Page MT88L89 BIT NAME DESCRIPTION b0 BURST Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode. When activated, the digital code representing a DTMF signal (see Table 1) can be written to the transmit register, which will result in a transmit DTMF tone burst and pause of equal durations (typically 51 msec). Following the pause, the status register will be updated (b1 - Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been enabled. When CP mode (Control Register A, b1) is enabled the normal tone burst and pause durations are extended from a typical duration of 51 msec to 102 msec. When BURST is high (de-activated) the transmit tone burst duration is determined by the TOUT bit (Control Register A, b0). b1 RxEN This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both circuits. A logic high deactivates and puts both receiver circuits into power-down mode. See Note 1 below. b2 S/D Single or Dual Tone Generation. A logic high selects the single tone output; a logic low selects the dual tone (DTMF) output. The single tone generation function requires further selection of either the row or column tones (low or high group) through the C/R bit (Control Register B, b3). b3 C/R Column or Row Tone Select. A logic high selects a column tone output; a logic low selects a row tone output. This function is used in conjunction with the S/D bit (Control Register B, b2). Table 7. Control Register B Description Note 1: When both TOUT and RxEN are asserted to power-down, the crystal oscillator and the Vref circuits are powered down. BIT NAME STATUS FLAG SET STATUS FLAG CLEARED b0 IRQ Interrupt has occurred. Bit one Interrupt is inactive. Cleared after (b1) or bit two (b2) is set. Status Register is read. b1 TRANSMIT DATA REGISTER EMPTY (BURST MODE ONLY) Pause duration has terminated and transmitter is ready for new data. Cleared after Status Register is read or when in non-burst mode. b2 RECEIVE DATA REGISTER Valid data is in the Receive Data Cleared after Status Register is FULL Register. read. b3 DELAYED STEERING Set upon the valid detection of the Cleared upon the detection of a absence of a DTMF signal. valid DTMF signal. Table 8. Status Register Description 4-133 11 Page

Páginas	Total 27 Páginas
PDF Descargar	[ Datasheet MT88L89.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
MT88L85	3V Integrated DTMFTransceiver	Mitel Networks Corporation
MT88L85	3V Integrated DTMFTransceiver	Zarlink Semiconductor
MT88L89	3V Integrated DTMFTransceiver with Adaptive Micro Interface	Mitel Networks Corporation
MT88L89	3V Integrated DTMFTransceiver with Adaptive Micro Interface	Zarlink Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar