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PDF MT4LC8M8C2 Data sheet ( Hoja de datos )
| Número de pieza | MT4LC8M8C2 | |
| Descripción | DRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MT4LC8M8C2 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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DRAM
8 MEG x 8
EDO DRAM
MT4LC8M8P4, MT4LC8M8C2
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions,
and packages
• 12 row, 11 column addresses (C2) or
13 row, 10 column addresses (P4)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-
compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
MARKING
C2
P4
• Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
DJ
TG
• Timing
50ns access
60ns access
-5
-6
• Refresh Rates
Standard Refresh (64ms period)
Self Refresh (128ms period)
None
S*
NOTE: 1. The 8 Meg x 8 EDO DRAM base number
differentiates the offerings in one place—
MT4LC8M8C2. The fifth field distinguishes the
address offerings: C2 designates 4K addresses and
P4 designates 8K addresses.
2. The “#” symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC8M8C2DJ-5
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
84ns
104ns
tRAC
50ns
60ns
tPC
20ns
25ns
tAA
25ns
30ns
tCAC
13ns
15ns
tCAS
8ns
10ns
PIN ASSIGNMENT (Top View)
32-Pin SOJ
32-Pin TSOP
VCC
DQ0
DQ1
DQ2
DQ3
NC
VCC
WE#
RAS#
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VSS
31 DQ7
30 DQ6
29 DQ5
28 DQ4
27 Vss
26 CAS#
VCC
DQ0
DQ1
DQ2
DQ3
NC
VCC
WE#
1
2
3
4
5
6
7
8
25 OE#
RAS# 9
24 NC/A12** A0 10
23 A11
A1 11
22 A10
21 A9
20 A8
19 A7
A2 12
A3 13
A4 14
A5 15
VCC 16
18 A6
17 VSS
**NC on C2 version and A12 on P4 version
32 VSS
31 DQ7
30 DQ6
29 DQ5
28 DQ4
27 VSS
26 CAS#
25 OE#
24 NC/A12**
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 VSS
8 MEG x 8 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC8M8C2DJ-x
MT4LC8M8C2DJ-x S
MT4LC8M8C2TG-x
MT4LC8M8C2TG-x S
MT4LC8M8P4DJ-x
MT4LC8M8P4DJ-x S
MT4LC8M8P4TG-x
MT4LC8M8P4TG-x S
REFRESH
ADDRESSING
4K
4K
4K
4K
8K
8K
8K
8K
PACKAGE REFRESH
SOJ
SOJ
TSOP
Standard
Self
Standard
TSOP
SOJ
SOJ
TSOP
TSOP
Self
Standard
Self
Standard
Self
x = speed
GENERAL DESCRIPTION
The 8 Meg x 8 DRAM is a high-speed CMOS, dy-
namic random-access memory devices containing
67,108,864 bits and designed to operate from 3V to
3.6V. The MT4LC8M8C2 and MT4LC8M8P4 are func-
tionally organized as 8,388,608 locations containing
eight bits each. The 8,388,608 memory locations are
arranged in 4,096 rows by 2,048 columns on the C2
version and 8,192 rows by 1,024 columns on the P4
version. During READ or WRITE cycles, each location is
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
1 page  
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Relative to VSS ................ -1V to +4.6V
Voltage on NC, Inputs or I/O Pins
Relative to VSS ....................................... -1V to +4.6V
Operating Temperature, TA (ambient) ... 0°C to +70°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 1W
8 MEG x 8
EDO DRAM
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Note: 1) (VCC = +3.3V ±0.3V)
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC
INPUT LEAKAGE CURRENT:
Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V);
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
IOUT = -2mA
OUTPUT LOW VOLTAGE:
IOUT = 2mA
OUTPUT LEAKAGE CURRENT:
Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V);
DQ is disabled and in High-Z state
SYMBOL
VCC
MIN
3
MAX UNITS NOTES
3.6 V
VIH
2 VCC + 0.3 V
26
VIL
-0.3 0.8
V 26
II -2 2 µA 27
VOH 2.4 – V
VOL – 0.4 V
IOZ -5 5 µA
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
5 Page 
RAS#
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
OE#
V
V
IH
IL
EARLY WRITE CYCLE
tRC
tRAS
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tRAD
tRAH
ROW
tAR
tASC
tCAH
tACH
tWCS
COLUMN
tCWL
tRWL
tWCR
tWCH
tWP
tDS tDH
VALID DATA
8 MEG x 8
EDO DRAM
tRP
ROW
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
tACH
tAR
tASC
tASR
tCAH
tCAS
tCRP
tCSH
tCWL
tDH
tDS
tRAD
MIN
12
38
0
0
8
8
5
38
8
8
0
9
-5
MAX
10,000
MIN
15
45
0
0
10
10
5
45
15
10
0
12
-6
MAX
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
tRAH
tRAS
tRC
tRCD
tRP
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
MIN
9
50
84
11
30
13
13
8
38
0
5
-5
MAX
10,000
MIN
10
60
104
14
40
15
15
10
45
0
5
-6
MAX
10,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8 Meg x 8 EDO DRAM
D20_2.p65 – Rev. 5/00
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MT4LC8M8C2.PDF ] | |
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