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PDF ICS2495 Data sheet ( Hoja de datos )
| Número de pieza | ICS2495 | |
| Descripción | Dual Video/Memory Clock Generator | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS2495
Dual Video/Memory Clock Generator
Features
• Low cost - eliminates need for multiple crystal clock • Buffered Xtal Out
oscillators in video display subsystems
• Integral Loop Filter components
• Mask-programmable frequencies
• Fast acquisition of selected frequencies, strobed or non-
• Pre-programmed versions for Industry Standard VGA
strobed
chips
• Guaranteed performance up to 135 MHz
• Glitch-free frequency transitions
• Excellent power supply rejection
• Internal clock remains locked when the external frequency
input is selected
• Low power CMOS device technology
• Advanced PLL for low phase-jitter
• Frequency change detection circuitry enhances new fre-
quency acquisition and eliminates problems caused by
• Small footprint - 16-pin DIP or SOIC
programs that rewrite frequency information
Description
Pin Configuration
The ICS2495 Clock Generator is an integrated circuit dual
phase-locked loop frequency synthesizer capable of generating
16 video frequencies and 4 memory clock frequencies for use
with high performance video display systems. Utilizing CMOS
technology to implement all linear, digital and memory func-
tions, the ICS2495 provides a low-power, small-footprint,
low-cost solution to the generation of video dot clocks. Outputs
are compatible with XGA, VGA, EGA, MCGA, CGA, MDA,
as well as the higher frequencies needed for advanced applica-
tions in desktop publishing and workstation graphics. Provi-
sion is made via a single level custom mask to implement
customer specific frequency sets. Phase-locked loop circuitry
permits rapid glitch-free transitions between clock frequencies.
In addition to providing 16 clock rates, the ICS2495 has
provisions to multiplex an externally-generated signal source
into the VCLK signal path. Internal phase-locked frequencies
continue to remain locked at their preset values when this mode
is selected. This feature permits instantaneous transition from
an external frequency to an internally-generated frequency.
Printed circuit boardtestingis simplified bythe useof thesemodes
as an external clock generated by the ATE tester can be fed
through, permitting synchronous testing of the entire system.
XTAL2
EXTFREQ
FS0
FS1
STROBE
FS2
FS3
MS0
1
2
3
4
5
6
7
8
16 XTAL1
15 VCLK
14 XTALOUT
13 VSS
12 VDD
11 N/C
10 MCLK
9 MS1
16-Pin DIP or SOIC
Notes:
1. ICS2495M(SOIC) pinout is identical to ICS2495N(DIP).
ICS2595RevA090694
1 page  
ICS2495
DC Characteristics at 5 Volts VDD
SYMBOL
VDD
VIL
VIH
IIH
VOL
VOH
IDD
RUP
Cin
Cout
PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage: VCLK, MCLK
XTALOUT
Output High Voltage: VCLK, MCLK
XTALOUT
Supply Current
Internal Pullup Resistors
Input Pin Capacitance
Output Pin Capacitance
MIN
4.75
VSS
2.0
-
-
-
2.4
2.4
-
50
-
-
MAX
5.25
0.8
V DD
10
0.4
0.4
-
-
30
-
8
12
AC Timing Characteristics
The following notes apply to all of the parameters presented in this section.
1. REFCLK = 14.318 MHz
2. TC = 1/FC
3. All units are in nanoseconds (ns).
4. Maximum jitter within a range of 30 µs after triggering on a 400 MHz scope.
5. Rise and fall time between 0.8 and 2.0 VDC unless otherwise stated.
6. Output pin loading = 15pF.
7. Duty cycle measured at 1.4 volts.
UNITS
V
V
V
µA
V
V
V
V
mA
K ohms
pF
pF
CONDITIONS
VDD = 5V
VDD = 5V
Vin = VCC
IOL = 8.0 mA
IOL = 4.0 mA
IOH = 8.0 mA
IOH = 4.0 mA
VDD = 5V
VIN = 0.0V
FC = 1 MHz
FC = 1 MHz
SYMBOL
Tpw
Tsu
Thd
Tr
Tf
-
-
-
-
PARAMETER
MIN
STROBE TIMING
Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe
20
10
10
MCLK and VCLK TIMINGS
Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for Pass Through
Frequency
Output Enable to Tristate
(into and out of) time
-
-
-
MAX
-
-
-
2
2
0.5
135
20
15
NOTES
Duty Cycle 40% min. to
60% max.
%
MHz
ns
ns
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ICS2495.PDF ] | |
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