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MT58L512L18P PDF даташит

Спецификация MT58L512L18P изготовлена ​​​​«Micron Semiconductor» и имеет функцию, называемую «(MT58Lxxxx) 8Mb SYNCBURST SRAM».

Детали детали

Номер произв MT58L512L18P
Описание (MT58Lxxxx) 8Mb SYNCBURST SRAM
Производители Micron Semiconductor
логотип Micron Semiconductor логотип 

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MT58L512L18P Даташит, Описание, Даташиты
om 8Mb: 512K x 18, 256K x 32/36
.c PIPELINED, SCD SYNCBURST SRAM
et4U MT58L512L18P, MT58L256L32P, MT58L256L36P;
8Mb SYNe CBURST MT58L512V18P, MT58L256V32P, MT58L256V36P
h 3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle
SRAM S Deselect
.DataFEATURES
w• Fast clock and OE# access times
w• Single +3.3V +0.3V/-0.165V power supply (VDD)
w• Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
m• SNOOZE MODE for reduced-power standby
o• Single-cycle deselect (Pentium® BSRAM-compatible)
• Common data inputs and data outputs
.c• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion
Uand address pipelining
• Clock-controlled and registered addresses, data
t4I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
e• Automatic power-down for portable applications
e• 100-pin TQFP package
• 165-pin FBGA package
h• Low capacitive bus loading
• x18, x32, and x36 versions available
SOPTIONS
ta• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
a5ns/10ns/100 MHz
• Configurations
.D3.3V I/O
512K x 18
256K x 32
256K x 36
w2.5V I/O
512K x 18
w256K x 32
256K x 36
w m• Packages
.co100-pin TQFP (2-chip enable)
100-pin TQFP (3-chip enable)
U165-pin, 13mm x 15mm FBGA
t4• Operating Temperature Range
eCommercial (0°C to +70°C)
eIndustrial (-40°C to +85°C)**
MARKING
-6
-7.5
-10
MT58L512L18P
MT58L256L32P
MT58L256L36P
MT58L512V18P
MT58L256V32P
MT58L256V36P
T
S
F*
None
IT
hPart Number Example:
ataSMT58L512L18PT-6
100-Pin TQFP1
165-Pin FBGA
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
GENERAL DESCRIPTION
The Micron® SyncBurstSRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x
18, 256K x 32, or 256K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock in-
put (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
ww.D8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
wMT58L512L18P_C.p65 – Rev. 2/02
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.









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MT58L512L18P Даташит, Описание, Даташиты
SA0, SA1, SAs
MODE
ADV#
CLK
ADSC#
ADSP#
BWb#
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
19
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
512K X 18
ADDRESS
REGISTER
19 17
2 SA0-SA1
BINARY Q1
COUNTER AND
LOGIC
CLR Q0
SA1'
SA0'
19
BYTE b
WRITE REGISTER
BYTE a
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
BYTE b
9
WRITE DRIVER
BYTE a
9
WRITE DRIVER
512K x 9 x 2
MEMORY 18
ARRAY
SENSE
AMPS
18
OUTPUT 18
REGISTERS
OUTPUT
BUFFERS
E
18
INPUT
18 REGISTERS
DQs
DQPa
DQPb
2
SA0, SA1, SAs
MODE
ADV#
CLK
ADSC#
ADSP#
BWd#
BWc#
BWb#
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
18
FUNCTIONAL BLOCK DIAGRAM
256K X 32/36
ADDRESS
REGISTER
18
16
SA0-SA1
18
SA1'
Q1
BINARY
COUNTER SA0'
CLR Q0
BYTE d
WRITE REGISTER
BYTE c
WRITE REGISTER
BYTE b
WRITE REGISTER
BYTE a
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
9
BYTE c
9
WRITE DRIVER
BYTE b
WRITE DRIVER
9
256K x 8 x 4
(x32)
256K x 9 x 4
(x36)
36
SENSE 36
AMPS
OUTPUT
REGISTERS
36
MEMORY
ARRAY
OUTPUT
BUFFERS
E
36
BYTE a
WRITE DRIVER
9
DQs
DQPa
DQPb
DQPc
DQPd
36
INPUT
REGISTERS
4
NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions, and timing diagrams
for detailed information.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.









No Preview Available !

MT58L512L18P Даташит, Описание, Даташиты
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
(GW#). Note that CE2# is not available on the
T Version.
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls
DQb pins and DQPb. During WRITE cycles on the x32
and x36 devices, BWa# controls DQa pins and DQPa;
BWb# controls DQb pins and DQPb; BWc# controls
DQc pins and DQPc; BWd# controls DQd pins and
DQPd. GW# LOW causes all bytes to be written. Parity
bits are only available on the x18 and x36 versions.
This device incorporates a single-cycle deselect fea-
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state tKQHZ nanoseconds after the rising edge
of clock.
Micron’s 8Mb SyncBurst SRAMs operate from a
+3.3V VDD power supply, and all inputs and outputs are
TTL-compatible. Users can choose either a 3.3V or 2.5V
I/O version. The device is ideally suited for Pentium
and PowerPC pipelined systems and systems that ben-
efit from a very wide, high-speed data bus. The device
is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-
wide applications.
Please refer to Micron’s Web site (www.micron.com/
sramds) for the latest data sheet.
TQFP PINOUTS
At the time of the writing of this data sheet, there are
two pinouts in the industry. Micron will support both
pinouts for this part.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 Rev. 2/02
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.










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