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PDF MT58L512L18D Data sheet ( Hoja de datos )
| Número de pieza | MT58L512L18D | |
| Descripción | (MT58Lxxxx) 8Mb SYNCBURST SRAM | |
| Fabricantes | Micron Semiconductor | |
| Logotipo |  |
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om 8Mb: 512K x 18, 256K x 32/36
.c 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
t4U ™
8SMRAbMSSYheNe CBURST MMTT5588LL521526LL1386DD, MT58L256L32D,3.3V VDD, 3.3V I/O, Pipelined, Double-
ta Cycle Deselect
.DaFEATURES
w• Fast clock and OE# access times
w• Single +3.3V +0.3V/-0.165V power supply (VDD)
w• Separate +3.3V isolated output buffer supply (VDDQ)
m• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
o• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and
.caddress pipelining
• Clock-controlled and registered addresses, data I/Os
and control signals
U• Internally self-timed WRITE cycle
t4• Burst control (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-pin TQFP package
e• 165-pin FBGA package
• Low capacitive bus loading
e• x18, x32, and x36 versions available
hOPTIONS
• Timing (Access/Cycle/MHz)
S3.5ns/6ns/166 MHz
ta4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
a512K x 18
256K x 32
.D256K x 36
• Packages
w100-pin TQFP (2-chip enable)
100-pin TQFP (3-chip enable)
165-pin, 13mm x 15mm FBGA
w• Operating Temperature Range
w mCommercial (0°C to +70°C)
oIndustrial (-40°C to +85°C)**
MARKING
-6
-7.5
-10
MT58L512L18D
MT58L256L32D
MT58L256L36D
T
S
F*
None
IT
U.cPart Number Example
t4MT58L512L18DT-7.5
ee* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
h** Industrial temperature range offered in specific speed grades and
.DataSconfigurations. Contact factory for more information.
100-Pin TQFP**
165-Pin FBGA
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs high-
speed, low-power CMOS designs that are fabricated us-
ing an advanced CMOS process.
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18,
256K x 32, or 256K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, active LOW chip enable (CE#), two additional
chip enables for easy depth expansion (CE2, CE2#), burst
control inputs (ADSC#, ADSP#, ADV#), byte write
enables (BWx#) and global write (GW#). Note that CE2#
is not available on the T Version.
ww8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
wMT58L512L18D_D.p65 – Rev. 2/02
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
1 page  
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
Pin Assignment (Top View)
100-Pin TQFP, 2-Chip Enable,
T Version
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
VSS
VDD
SA
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81 50
82 49
83 48
84 47
85 46
86 45
87 44
88 43
89 42
x1890 41
91 40
92 39
93 38
94 37
95 36
96 35
97 34
98 33
99 32
100 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
SA
SA
SA
SA
SA
SA
NF
NF
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
VSS
VDD
SA
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81 50
82 49
83 48
84 47
85 46
86 45
87 44
88 43
89 42
x32/x3690 41
91 40
92 39
93 38
94 37
95 36
96 35
97 34
98 33
99 32
100 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
SA
SA
SA
SA
SA
SA
NF
NF
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
5 Page 
8Mb: 512K x 18, 256K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
FBGA PIN DESCRIPTIONS (continued)
x18 x32/x36 SYMBOL TYPE
DESCRIPTION
9A 9A ADV# Input Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on ADV# effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
9B 9B ADSP# Input Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
8A 8A ADSC# Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
1R 1R MODE Input Mode: This input selects the burst sequence. A LOW on this
(LB0#)
input selects “linear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is
operating.
(a) 10J, 10K, (a) 10J, 10K,
10L, 10M, 11D, 10L, 10M, 11J,
11E, 11F, 11G 11K, 11L, 11M
(b) 1J, 1K,
1L, 1M, 2D,
2E, 2F, 2G
(b) 10D, 10E,
10F, 10G, 11D,
11E, 11F, 11G
(c) 1D, 1E,
1F, 1G, 2D,
2E, 2F, 2G
(d) 1J, 1K, 1L,
1M, 2J, 2K,
2L, 2M
DQa
DQb
DQc
DQd
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;
Output Byte “b” is associated with DQbs. For the x32 and x36 versions,
Byte “a” is associated with DQas; Byte “b” is associated with DQbs;
Byte “c” is associated with DQcs; Byte “d” is associated with DQds.
Input data must meet setup and hold times around the rising edge
of CLK.
11C 11N NF/DQPa NF/ No Funciton/Parity Data I/Os: On the x32 version, these are No
1N 11C NF/DQPb I/O Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”
–
1C NF/DQPc
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
–
1N NF/DQPd
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F,
4G, 4H, 4J, 4G, 4H, 4J,
4K, 4L, 4M, 4K, 4L, 4M,
8D, 8E, 8F, 8D, 8E, 8F,
8G, 8H, 8J, 8G, 8H, 8J,
8K, 8L, 8M 8K, 8L, 8M
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
(continued on next page)
8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L512L18D_D.p65 – Rev. 2/02
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MT58L512L18D.PDF ] | |
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