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AN10E40 PDF даташит

Спецификация AN10E40 изготовлена ​​​​«Anadigm» и имеет функцию, называемую «Field Programmable Analog Array».

Детали детали

Номер произв AN10E40
Описание Field Programmable Analog Array
Производители Anadigm
логотип Anadigm логотип 

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AN10E40 Даташит, Описание, Даташиты
AN10E40
Field Programmable Analog Array
The AN10E40 brings to analog what FPGAs brought to digital; extremely rapid production and prototype circuit
realization with field re-programmability. The AN10E40 consists of a 4 x 5 matrix of fully configurable switched
capacitor cells, enmeshed in a fabric of programmable interconnect resources. These programmable features are
directed by an on-chip SRAM configuration memory. The SRAM configuration memory is initialized on power up
via an off chip serial PROM or through the AN10E40Õs standard microprocessor peripheral interface.
A configuration memory image is easily constructed using the companion AnadigmDesigner¨ software which
includes an extensive library of adjustable, proven, pre-built functions. The configurable analog blocks are often
consumed one at a time, though some of the more complex library functions may consume two or more blocks.
Specialized IO cells surround the core to bring your analog signals in and out of the array.
The AN10E40 coupled with the intuitive AnadigmDesigner¨ software gives both digital and analog designers a
mcompetitive advantage in designing analog circuits that canÕt really be compared to any other design system in
existence. Quickly constructed, accurate, drift free, temperature compensated and programmable analog circuits
oare now yours. Imagine the power of programmable with the versatility of analog.
.cBenefits
UExtremely Rapid Analog Design Ð Minutes not weeks to re-spin a new design idea
t4In Circuit Programmable Ð Behavior can be changed as fast as 125 microseconds
Re-Configurable Using Conventional Logic, Serial PROMs or Microcontrollers
eExtremely Stable over Voltage and Temperature
Flexible Internal Clock and Routing Resources
No Component Aging
No More Trimming Components
eReliable and Repeatable Performance
No More Tuning Components
ShConfig. Logic
Configuration Data Shift Register
taCAB
CAB
CAB
CAB
CAB
.DaCAB
CAB
CAB
CAB
CAB
www CAB
CAB
CAB
CAB
CAB
CAB
CAB
CAB
CAB
CAB
Vref
I OI OI OI OI O
XY Z XY Z XY Z XYZ XY Z
Anadigm¨
UM020800-U005









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AN10E40 Даташит, Описание, Даташиты
Anadigm¨ reserves the right to make any changes without further notice to any
products herein. Anadigm¨ makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does
Anadigm¨ assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including with limitation
consequential or incidental damages. ÒTypicalÓ parameters can and do vary in
different applications. All operating parameters, including ÒTypicalsÓ must be
validated for each customer application by customerÕs technical experts.
Anadigm¨ does not convey any license under its patent rights nor the rights of
others. Anadigm¨ products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which
the failure of the Anadigm¨ product could create a situation where personal injury
or death may occur. Should buyer purchase or use Anadigm¨ product for any
such unintended or unauthorized application, buyer shall indemnify and hold
Anadigm¨ and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim
alleges that Anadigm¨ was negligent regarding the design or manufacture of the
part.
Copyright © Anadigm¨ 2002
All Rights Reserved
Anadigm¨
UM020800-U005









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AN10E40 Даташит, Описание, Даташиты
Table of Contents
AN10E40 Data Manual i
Features of AN10E40 ...................................................................................................................................................... 1
Available IPmodule Functions ......................................................................................................................................... 1
How It Works .................................................................................................................................................................... 1
AN10E40 Architecture ..................................................................................................................................................... 2
The Configurable Analog Block....................................................................................................................................... 3
A Quick Review of Switched Capacitor Circuits ......................................................................................................... 3
CAB Details .................................................................................................................................................................. 4
Routing Resources........................................................................................................................................................... 4
Clock Generation ............................................................................................................................................................. 4
Voltage Reference ........................................................................................................................................................... 5
Voltage Mid-Rail Generator ............................................................................................................................................. 5
Analog Input Output Cell.................................................................................................................................................. 6
Sallen Key Filtering ...................................................................................................................................................... 6
2nd Order Sallen-Key Filter for Output Smoothing ...................................................................................................... 7
4th Order Sallen-Key Filter for Output Smoothing ....................................................................................................... 7
2nd Order Sallen-Key Filter for Input Anti-Aliasing ...................................................................................................... 7
4th Order Sallen-Key Filter for Input Anti-Aliasing ....................................................................................................... 8
Configuration Engine ....................................................................................................................................................... 9
Mode 0 Ð Micro Mode (Parallel Loading) .................................................................................................................. 10
Micro Mode Maximum Data Transfer Rate ........................................................................................................... 12
Function Register (RS=0) and Data/Status Register (RS=1) ............................................................................... 12
Sending the Reset Device Command ................................................................................................................... 12
Micro Mode - Configuration Sequence .................................................................................................................. 13
Organization of Configuration Memory - The ASCII Hex Configuration File Format .......................................... 14
Mode 1 Ð Boot from ROM (BFR Mode)..................................................................................................................... 15
BFR Timing................................................................................................................................................................. 16
Configuration Clock .................................................................................................................................................... 17
Reset Sequences........................................................................................................................................................... 18
Analog Power On Reset (APOR) & Power On Reset (POR) ................................................................................... 18
Internal Reset Activity................................................................................................................................................. 18
External Reset Assertion............................................................................................................................................ 18
Mechanical ..................................................................................................................................................................... 18
Package Details.......................................................................................................................................................... 18
Pin Out Description .................................................................................................................................................... 19
Package Pin Electrical Characterization ................................................................................................................... 22
Powers, Grounds and Bypassing .................................................................................................................................. 22
Recommended Configuration for Power & Ground .................................................................................................. 22
AVDD and AVSS ........................................................................................................................................................ 22
SVDD and SVSS ........................................................................................................................................................ 22
BVDD and BVSS ........................................................................................................................................................ 23
ESD_VDD and ESD_VSS ......................................................................................................................................... 23
CFG_VDD and CFG_VSS ......................................................................................................................................... 23
OPAMVMR and CEXT ............................................................................................................................................... 23
The AN10E40 in Split Supply Systems ..................................................................................................................... 23
Characterized Electrical Parameters............................................................................................................................. 24
Absolute Maximum Ratings ....................................................................................................................................... 24
Recommended Operating Conditions ....................................................................................................................... 24
Power Consumption ................................................................................................................................................... 24
Digital Interface Characteristics ................................................................................................................................. 25
VMR (Voltage Mid-Rail) ............................................................................................................................................. 25
Vref (Reference Voltage) ........................................................................................................................................... 26
Analog Input/Output Buffer ........................................................................................................................................ 26
I/O Cell Bandwidth (Unity gain buffer) ....................................................................................................................... 27
I/O Buffer Cell Configured as a Sallen-Key Filter ..................................................................................................... 27
Analog Core Cell (C.A.B. Configurable Analog Block) Amplifier.............................................................................. 28
Typical Performance Examples..................................................................................................................................... 29
Anadigm¨
UM020800-U005










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