3511 PDF даташит
Спецификация 3511 изготовлена «Unisonic Technologies» и имеет функцию, называемую «PC Power Supply Supervisors». |
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Детали детали
Номер произв | 3511 |
Описание | PC Power Supply Supervisors |
Производители | Unisonic Technologies |
логотип |
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UNISONIC TECHNOLOGIES CO., LTD
3511
PC POWER SUPPLY
SUPERVISORS
DESCRIPTION
The UTC 3511 is designed to provide the voltage, and current
supervisor function, power good output (PGO), fault protection
latch (FPL_N), and protection detector function (PDON_N) control
for switching power systems.
For supervisor function, it provides the over voltage detector
(OVD) monitoring for 3.3V, 5V, 12V; the under voltage detector
(UVD) monitoring for 3.3V, 5V. When 3.3V or 5V voltage is
decreasing to 2.69V, 4.3V respectively, the under voltage
detector (UVD) function will be enabled to reset the PGO signal
from high to low,and the FPL_N is latched HIGH. When 3.3V, 5V
or 12V voltage is increasing to 3.9V, 6.1V or 13.4V respectively,
the over voltage detector (OVD) function will be enabled to reset
the PGO signal from high to low, and the FPL_N is latched HIGH.
To achieve better immunity for lighting surge glitch and to
prevent accidental power shut down during dynamic loading
condition, the de-bounce time for UVD and OVD is 73us. The
power supply is turned on after 38mS de-bounce time when
FPL_N signal is set from high to low.
FEATURES
* Over Voltage Detector (OVD) for 3.3V, 5V, 12V.
* Under Voltage Detector (UVD) for 3.3V, 5V.
* Open Drain Output for PGO and FPL_N.
* 300 ms power good delay.
* 75 ms delay for 3.3V and 5V turn on.
* 38 ms PDON_N control De-bounce.
* 2.4 ms PDON_N control to FPL_N turn-off delay.
* De-bounce time 73 μs for UVD/OVD.
* Wide supply voltage range from 4V ~ 15V.
■ ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
3511L-D08-T
3511G-D08-T
- 3511G-S08-R
Package
DIP-8
SOP-8
CMOS IC
DIP-8
SOP-8
Packing
Tube
Tape Reel
www.unisonic.com.tw
Copyright © 2015 Unisonic Technologies Co., Ltd
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3511
MARKING
DIP-8
SOP-8
CMOS IC
PIN CONFIGURATION
PGI 1
GND 2
FPL_N 3
PDON_N 4
8 PGO
7 VDD
6 V5
5 V33
PIN DESCRIPTION
PIN No.
1
2
3
4
5
6
7
8
PIN NAME
PGI
GND
FPL-N
PDON-N
V33
V5
VDD
PGO
TYPE
I
P
O
I
I
I
I
O
DESCRIPTION
Power good input pin
Ground
Fault protection latch output pin (open drain output)
Protection detector function ON/OFF control input pin
3.3V input pin
5V input pin
Supply voltage/12V input pin
Power good output pin(open drain output)
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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3511
BLOCK DIAGRAM
VDD
150μA
Power On Reset POR
Vcc Low Voltage LVRST
Clock
Generator
CLK
PWR
3.6V
PDON_N
V33
V5
+- UN
+- OV
+- UN
+- OV
CLK PWR
38ms
debounce
RST
CLK
CLR
2.4ms
delay
CLK RWR
CLR 75ms
delay
PWR
CLK RST
73 μs
debounce
R
SQ
VDD
+-OV
PGI +-UN
1.2V
CLK RST
73μs
debounce
CLK
CLR
300ms
delay
CMOS IC
FPL_N
VDD
PGO
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
3 of 8
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