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PDF MT90823 Data sheet ( Hoja de datos )
| Número de pieza | MT90823 | |
| Descripción | 3V Large Digital Switch | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MT90823 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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MT90823
3V Large Digital Switch
Data Sheet
Features
• 2,048 × 2,048 channel non-blocking switching at
8.192 Mb/s
• Per-channel variable or constant throughput
delay
• Automatic identification of ST-BUS/GCI interfaces
• Accept ST-BUS streams of 2.048, 4.096 or 8.192
Mb/s
• Automatic frame offset delay measurement
• Per-stream frame delay offset programming
• Per-channel high impedance output control
• Per-channel message mode
• Control interface compatible to Motorola non-
multiplexed CPUs
• Connection memory block programming
• 3.3V local I/O with 5V tolerant inputs and TTL-
compatible outputs
• IEEE-1149.1 (JTAG) Test Port
Applications
• Medium and large switching platforms
• CTI application
• Voice/data multiplexer
• Digital cross connects
• ST-BUS/GCI interface functions
• Support IEEE 802.9a standard
February 2003
Ordering Information
MT90823AP
MT90823AL
MT90823AB
MT90823AG
84 Pin PLCC
100 Pin MQFP
100 Pin LQFP
120 Pin PBGA
-40°C to +85°C
Description
The MT90823 Large Digital Switch has a non-blocking
switch capacity of: 2,048 x 2,048 channels at a serial bit
rate of 8.192 Mb/s; 1,024 x 1,024 channels at 4.096
Mb/s; and 512 x 512 channels at 2.048 Mb/s. The
device has many features that are programmable on a
per stream or per channel basis, including message
mode, input offset delay and high impedance output
control.
Per stream input delay control is particularly useful for
managing large multi-chip switches that transport both
voice channel and concatenated data channels.
In addition, the input stream can be individually
calibrated for input frame offset using a dedicated pin.
VDD VSS
TMS TDI TDO TCK TRST IC RESET
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
Serial
to
Parallel
Converter
Timing
Unit
Test Port
Loopback
Multiple Buffer
Data Memory
Internal
Registers
Output
MUX
CoMnenmecotriyon
Parallel
to
Serial
Converter
Microprocessor Interface
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
CLK F0i FE/ WFPS
HCLK
AS/
ALE
IM
DS/
RD
CS
R/W
/WR
A7-A0 DTA D15-D8/ CSTo
AD7-AD0
Figure 1 - Functional Block Diagram
1
1 page  
Data Sheet
MT90823
Pin Description (continued)
Pin #
84 100 100
PLCC MQFP LQFP
35 8
5
120
BGA
N3
36 9
37 10
6
7
M4
N4
38 11
8
M5
39 12
9
N5
40 13 10
M6
41 - 14-21 11 -
48 18
N6,M7,N7,N8,
M8,N9,M9,N10
49 22 19
N11
Name
Description
TDO
TCK
TRST
IC
RESET
WFPS
A0 - A7
DS/RD
Test Serial Data Out (3.3V Output): JTAG serial data
is output on this pin on the falling edge of TCK. This pin
is held in high impedance state when JTAG scan is not
enabled.
Test Clock (5V Tolerant Input): Provides the clock to
the JTAG test logic.
Test Reset (3.3V Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should
be pulsed low on power-up, or held low, to ensure that
the MT90823 is in the normal functional mode.
Internal Connection (3.3V Input with internal pull-
down): Connect to VSS for normal operation. This pin
must be low for the MT90823 to function normally and
to comply with IEEE 1149 (JTAG) boundary scan
requirements.
Device Reset (5V Tolerant Input): This input (active
LOW) puts the MT90823 in its reset state to clear the
device internal counters, registers and bring STo0 - 15
and microport data outputs to a high impedance state.
The time constant for a power up reset circuit must be a
minimum of five times the rise time of the power supply.
In normal operation, the RESET pin must be held low
for a minimum of 100nsec to reset the device.
Wide Frame Pulse Select (5V Tolerant Input): When
1, enables the wide frame pulse (WFP) Frame
Alignment interface. When 0, the device operates in
ST-BUS/GCI mode.
Address 0 - 7 (5V Tolerant Input): When non-
multiplexed CPU bus operation is selected, these lines
provide the A0 - A7 address lines to the internal
memories.
Data Strobe / Read (5V Tolerant Input): For Motorola
multiplexed bus operation, this input is DS. This active
high DS input works in conjunction with CS to enable
the read and write operations.
For Motorola non-multiplexed CPU bus operation, this
input is DS. This active low input works in conjunction
with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This
active low input sets the data bus lines (AD0-AD7, D8-
D15) as outputs.
Zarlink Semiconductor Inc.
5
5 Page 
Data Sheet
MT90823
Delay Through the MT90823
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform time-slot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice application, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant throughput delay to maintain
the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected in the V/C bit of the
connection memory.
Variable Delay Mode (V/C bit = 0)
The delay in this mode is dependent only on the combination of source and destination channels. It is independent
of input and output streams. The minimum delay achievable in the MT90823 is three time-slots. When the input
channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame
(channel n, frame p+1). The same frame delay occurs if the input channel n is switched to output channel n+1 or
n+2. When input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same
frame. Table 2 shows the possible delays for the MT90823 in the variable delay mode.
Constant Delay Mode (V/C bit = 1)
In this mode, frame integrity is maintained in all switching configurations by using a multiple data memory buffer.
Input channel data written into the data memory buffers during frame n will be read out during frame n+2.
In the MT90823, the minimum throughput delay achievable in the constant delay mode is one frame. For example,
in 2 Mb/s mode, when input time-slot 31 is switched to output time-slot 0. The maximum delay of 94 time-slots
occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 3.
Microprocessor Interface
The MT90823 provides a parallel microprocessor interface for non-multiplexed or multiplexed bus structures. This
interface is compatible with Motorola non-multiplexed and multiplexed buses.
If the IM pin is low, the MT90823 microprocessor interface assumes Motorola non-multiplexed bus mode. If the IM
pin is high, the device micro- processor interface accepts two different timing modes (mode1 and mode2) which
allows direct connection to multiplexed microprocessors.
The microprocessor interface automatically identifies the type of microprocessor bus connected to the MT90823.
This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing
connected to the MT90823. If DS/RD is high at the falling edge of AS/ALE, then the mode 1 multiplexed timing is
selected. If DS/RD is low at the falling edge of AS/ALE, then the mode 2 multiplexed bus timing is selected.
Input Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Delay for Variable Throughput Delay Mode
(m - output channel number)
(n - input channel number))
m<n
m = n, n+1, n+2
32 - (n-m) time-slots
m-n + 32 time-slots
64 - (n-m) time-slots
m-n + 64 time-slots
128 - (n-m) time-slots
m-n + 128 time-slots
Table 2 - Variable Throughput Delay Value
m > n+2
m-n time-slots
m-n time-slots
m-n time-slots
Zarlink Semiconductor Inc.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT90823.PDF ] | |
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