MTD2955V Datasheet PDF ( Pinout ) - TMOS POWER FET 12 AMPERES 60 VOLTS RDS(on) = 0.230 OHM

MTD2955V Datasheet PDF - Motorola Semiconductors

Part Number	*MTD2955V*
Description	TMOS POWER FET 12 AMPERES 60 VOLTS RDS(on) = 0.230 OHM
Manufacturers	Motorola Semiconductors
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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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™Designer's Data Sheet

TMOS V™

Power Field Effect Transistor

DPAK for Surface Mount

P–Channel Enhancement–Mode Silicon Gate

TMOS V is a new technology designed to achieve an on–resis-

tance area product about one–half that of standard MOSFETs. This

new technology more than doubles the present cell density of our

50 and 60 volt TMOS devices. Just as with our TMOS E–FET

designs, TMOS V is designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high

speed switching applications in power supplies, converters and

power motor controls, these devices are particularly well suited for

bridge circuits where diode speed and commutating safe operating

areas are critical and offer additional safety margin against

unexpected voltage transients.

New Features of TMOS V

• On–resistance Area Product about One–half that of Standard

MOSFETs with New Low Voltage, Low RDS(on) Technology

• Faster Switching than E–FET Predecessors

MTD2955V

TMOS POWER FET

12 AMPERES

60 VOLTS

RDS(on) = 0.230 OHM

CASE 369A–13, Style 2

S DPAK Surface Mount

Features Common to TMOS V and TMOS E–FETS

• Avalanche Energy Specified

• IDSS and VDS(on) Specified at Elevated Temperature

• Static Parameters are the Same for both TMOS V and TMOS E–FET

• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,

Add T4 Suffix to Part Number

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating

Symbol

Value

Unit

Drain–to–Source Voltage

Drain–to–Gate Voltage (RGS = 1.0 MΩ)

Gate–to–Source Voltage — Continuous

Gate–to–Source Voltage — Non–repetitive (tp ≤ 10 ms)

VDSS

VDGR

VGS

VGSM

± 15

± 25

Vdc

Vpk

Drain Current — Continuous

Drain Current — Continuous @ 100°C

Drain Current — Single Pulse (tp ≤ 10 µs)

ID 12 Adc

ID 8.0

IDM 42 Apk

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ 25°C(1)

PD 60 Watts

0.4 W/°C

2.1 Watts

Operating and Storage Temperature Range

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.0 mH, RG = 25 Ω)

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient

Thermal Resistance — Junction to Ambient(1)

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

TJ, Tstg

EAS

RθJC

RθJA

– 55 to 175

216

2.5

100

71.4

260

°C

°C/W

°C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

REV 3

10 30

9 QT 27

8 Q1

7 VGS 21

6 18

5 15

4 12

3 ID = 12 A 9

2 TJ = 25°C 6

1 Q3

VDS 3

00 2

8 10 12 14 16 18 20

QT, TOTAL CHARGE (nC)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

1000

VDD = 30 V

ID = 12 A

VGS = 10 V

TJ = 25°C

100

td(off)

10 td(on)

MTD2955V

1 10 100

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

11 VGS = 0 V

10 TJ = 25°C

0.5 0.7 0.9 1.1 1.3 1.5 1.7

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

1.9

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is for-

ward biased. Curves are based upon maximum peak junc-

tion temperature and a case temperature (TC) of 25°C. Peak

repetitive pulsed power limits are determined by using the

thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance–General

Data and Its Use.”

Switching between the off–state and the on–state may tra-

verse any load line provided neither rated peak current (IDM)

nor rated voltage (VDSS) is exceeded and the transition time

(tr,tf) do not exceed 10 µs. In addition the total power aver-

aged over a complete switching cycle must not exceed

(TJ(MAX) – TC)/(RθJC).

A Power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-

sipated in the transistor while in avalanche must be less than

the rated limit and adjusted for operating conditions differing

from those specified. Although industry practice is to rate in

terms of energy, avalanche energy capability is not a con-

stant. The energy rating decreases non–linearly with an in-

crease of peak current in avalanche and peak junction

temperature.

Although many E–FETs can withstand the stress of drain–

to–source avalanche at currents up to rated pulsed current

(IDM), the energy rating is specified at rated continuous cur-

rent (ID), in accordance with industry custom. The energy rat-

ing must be derated for temperature as shown in the

accompanying graph (Figure 12). Maximum energy at cur-

rents below rated continuous ID can safely be assumed to

equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data

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