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PDF MPC7450 Data sheet ( Hoja de datos )
| Número de pieza | MPC7450 | |
| Descripción | Micricontroller | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Advance Information
Freescale Semiconductor, Inc.
MPC7450EC/D
Rev. 4, 11/2001
MPC7450
RISC Microprocessor
Hardware Specifications
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Section 1.7, “Pinout Listings for the 483 CBGA Package”
31
Section 1.8, “Package Description”
34
Section 1.9, “System Design Information”
36
Section 1.10, “Document Revision History”
48
Section 1.11, “Ordering Information”
49
To locate any published updates for this document, refer to the website at
http://www.motorola.com/semiconductors
1.1 Overview
The MPC7450 is the third implementation of the fourth generation (G4) microprocessors from
Motorola. The MPC7450 implements the full PowerPC 32-bit architecture and is targeted at
networking and computing systems applications. The MPC7450 consists of a processor core,
a 256-Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3
cache through a dedicated high bandwidth interface.
Figure 1 shows a block diagram of the MPC7450. The core is a high-performance superscalar
design supporting a double-precision floating-point unit and a SIMD multimedia unit. The
memory storage subsystem supports the MPX bus interface to main memory and other system
resources. The L3 interface supports 1 or 2 Mbytes of external SRAM for L3 cache data.
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
Features
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
• Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
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— On-chip, 256-Kbyte, 8-way set associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total 9-cycle load latency for an L1 data cache miss that hits in L2
— Pseudo least-recently-used (PLRU) replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache
• Level 3 (L3) cache interface
— Provides critical double-word forwarding to the requesting unit
— Internal L3 cache controller and tags
— External data SRAMs
— Support for 1- and 2-Mbyte L3 caches
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte (1 M) or 128-byte (2 M) sectored line size
— Private memory capability for half (1-Mbyte minimum) or all of the L3 SRAM space
— Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined
synchronous Burst SRAMs, and pipelined (register-register) Late Write synchronous Burst
SRAMs
MOTOROLA
MPC7450 RISC Microprocessor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
5
5 Page 
Freescale Semiconductor, Inc.
Electrical and Thermal Characteristics
Figure 2 shows the undershoot and overshoot voltage on the MPC7450.
OVDD/GVDD + 20%
OVDD/GVDD + 5%
OVDD/GVDD
VIH
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OVDD or GVDD power pins.
Table 3. Input Threshold Voltage Setting
BVSEL Signal
Processor Bus Input
Threshold is Relative to:
L3VSEL Signal
L3 Bus Input Threshold is
Relative to:
Notes
0
1.8 V
0
1.8 V
1, 4
¬HRESET
Not Available
¬HRESET
1.5 V
1, 3
HRESET
2.5 V
HRESET
2.5 V
1, 2
1
2.5 V
1
2.5 V
1
Notes:
1. Caution: The input threshold selection must agree with the OVDD/GVDD voltages supplied. See notes in Table 2.
2. To select the 2.5-V threshold option for the processor bus, BVSEL should be tied to HRESET so that the two
signals change state together. Similarly, to select 2.5 V for the L3 bus, tie L3VSEL to HRESET. This is the preferred
method for selecting this mode of operation.
3. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.
4. If used, pulldown resistors should be less than 250 Ω .
MOTOROLA
MPC7450 RISC Microprocessor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MPC7450.PDF ] | |
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