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PDF MT8LDT864 Data sheet ( Hoja de datos )
| Número de pieza | MT8LDT864 | |
| Descripción | SMALL-OUTLINE DRAM MODULE | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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SMALL-OUTLINE
DRAM MODULE
4, 8 MEG x 64
DRAM SODIMMs
MT4LDT464H (X)(S), MT8LDT864H (X)(S)
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/datasheets/datasheet.html
FEATURES
• JEDEC pinout in a 144-pin, small-outline, dual in-
line memory module (SODIMM)
• 32MB (4 Meg x 64) and 64MB (8 Meg x 64)
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Optional Self Refresh Mode (S)
• Serial presence-detect (SPD)
OPTIONS
• Package
144-pin SODIMM (gold)
MARKING
G
• Timing
50ns access
60ns access
-5
-6
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
None
X
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
*Contact factory for availability
None
S*
KEY TIMING PARAMETERS
FPM Operating Mode
SPEED
-5
-6
tRC
90ns
110ns
tRAC
50ns
60ns
tPC
30ns
35ns
tAA
25ns
30ns
tCAC
13ns
15ns
tRP
30ns
40ns
EDO Operating Mode
SPEED
-5
-6
tRC
84ns
104ns
tRAC
50ns
60ns
tPC
20ns
25ns
tAA
25ns
30ns
tCAC
13ns
15ns
tCAS
8ns
10ns
PIN ASSIGNMENT (Front View)
144-Pin Small-Outline DIMM
(I-1; 32MB)
(I-2; 64MB)
PIN FRONT PIN BACK PIN FRONT PIN BACK
1 VSS 2 VSS 73 OE# 74 RFU
3 DQ0 4 DQ32 75 VSS 76 VSS
5 DQ1 6 DQ33 77 RSVD 78 RSVD
7 DQ2 8 DQ34 79 RSVD 80 RSVD
9 DQ3 10 DQ35 81 VDD 82 VDD
11 VDD 12 VDD 83 DQ16 84 DQ48
13 DQ4 14 DQ36 85 DQ17 86 DQ49
15 DQ5 16 DQ37 87 DQ18 88 DQ50
17 DQ6 18 DQ38 89 DQ19 90 DQ51
19 DQ7 20 DQ39 91 VSS 92 VSS
21 VSS 22 VSS 93 DQ20 94 DQ52
23 CAS0# 24 CAS4# 95 DQ21 96 DQ53
25 CAS1# 26 CAS5# 97 DQ22 98 DQ54
27 VDD 28 VDD 99 DQ23 100 DQ55
29 A0 30 A3 101 VDD 102 VDD
31 A1 32 A4 103 A6 104 A7
33 A2 34 A5 105 A8 106 A11
35 VSS 36 VSS 107 VSS 108 VSS
37 DQ8 38 DQ40 109 A9 110 NC (A12)
39 DQ9 40 DQ41 111 A10 112 NC (A13)
41 DQ10 42 DQ42 113 VDD 114 VDD
43 DQ11 44 DQ43 115 CAS2# 116 CAS6#
45 VDD 46 VDD 117 CAS3# 118 CAS7#
47 DQ12 48 DQ44 119 VSS 120 VSS
49 DQ13 50 DQ45 121 DQ24 122 DQ56
51 DQ14 52 DQ46 123 DQ25 124 DQ57
53 DQ15 54 DQ47 125 DQ26 126 DQ58
55 VSS 56 VSS 127 DQ27 128 DQ59
57 RSVD 58 RSVD 129 VDD 130 VDD
59 RSVD 60 RSVD 131 DQ28 132 DQ60
61 RFU 62 RFU 133 DQ29 134 DQ61
63 VDD 64 VDD 135 DQ30 136 DQ62
65 RFU 66 RFU 137 DQ31 138 DQ63
67 WE# 68 RFU 139 VSS 140 VSS
69 RAS0# 70
NC 141 SDA 142 SCL
71 NC 72 NC 143 VDD 144 VDD
NOTE: Symbols in parentheses are not used on these modules but
may be used for other modules in this product family. They
are for reference only.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
1 page  
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various DRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations be-
tween the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals.
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ures 1 and 2).
4, 8 MEG x 64
DRAM SODIMMs
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop con-
dition, which is a LOW-to-HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the SPD device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to
indicate successful data transfers. The transmitting
device, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
The SPD device will always respond with an ac-
knowledge after recognition of a start condition and
its slave address. If both the device and a WRITE
SCL SCL
SDA
DATA STABLE
DATA
DATA STABLE
CHANGE
Figure 1
Data Validity
SDA
START
BIT
STOP
BIT
Figure 2
Definition of Start and Stop
SCL from Master
89
Data Output
from Transmitter
Data Output
from Receiver
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
Acknowledge
Figure 3
Acknowledge Response From Receiver
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
5 Page 
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (VDD = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS#)
READ command setup time
Refresh period (4,096 cycles)
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time exiting Self Refresh
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time
RAS# to WE# delay time
WRITE command to RAS# lead time
Transition time (rise or fall)
WRITE command hold time
WRITE command hold time (referenced to RAS#)
WE# command setup time
WRITE command pulse width
WE# hold time (CBR Refresh)
WE# setup time (CBR Refresh)
SYMBOL
tRC
tRCD
tRCH
tRCS
tREF
tRP
tRPC
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
tWCS
tWP
tWRH
tWRP
MIN
90
18
0
0
30
0
90
0
13
131
73
13
2
8
40
0
8
10
10
-5
MAX
64
50
4, 8 MEG x 64
DRAM SODIMMs
MIN
110
20
0
0
40
0
105
0
15
155
85
15
2
10
45
0
10
10
10
-6
MAX
64
50
UNITS
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
14
16
16
27
27
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT8LDT864.PDF ] | |
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