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PDF AN7187 Data sheet ( Hoja de datos )
| Número de pieza | AN7187 | |
| Descripción | Clock and Synchronization Signals | |
| Fabricantes | Philips | |
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Philips Semiconductors
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
Author: Leo Warmuth
1.0 INTRODUCTION
The devices of the SAA7187/88 family of
video encoders can be used in a variety of
applications differing regarding the signal flow
of timing information. Video timing is defined
by clock signals, synchronization signals and
blanking signals. The video encoder ICs can
generate these signals by itself (master
mode), or can accept them as input (slave
mode). The master/slave characteristic can
be chosen independently for clock and
sync-signals.
This application note describes the various
clock and synchronization signals, their
functions, and how to select and program
them. The timing relation of some of these
signals is programmable. An application
example shows a possible configuration.
2.0 CLOCK LLC AND CREF
SIGNAL
The SAA7187/88 has two clock signals: LLC
and CREF, functionally compatible with other
Philips digital video processing circuits. LLC
on pin 38 is the Line-Locked-Clock in double
pixel clock frequency. CREF on pin 39 is the
clock qualifier signal, accompanying LLC, to
indicate on which LLC edges the 16 bit wide
YUV data stream transports valid data. CREF
is continuously toggling in pixel rate
frequency, but is not meant as pixel clock.
The transitions of CREF have to maintain
certain setup and hold times relative to clock
LLC (see data sheet). The digital encoder ICs
can generate and provide (drive) the clock
signals by its own by means of the built-in
crystal oscillator, or receive the clock signals
from external. In remote genlock mode, LLC
and CREF can be fed from one of the Philips
digital decoder (DMSD), but must then be
accompanied by RTC signal (real time control
information).
2.1 Built-in clock signal
generator
SAA7187/88 has built-in an optional crystal
oscillator for LLC frequency. A crystal with
double pixel clock frequency as base
frequency, or as third harmonic frequency,
with appropriate auxiliary circuitry, can be
connected between the pins XTALi (input,
pin 41) and XTALo (output, pin 40). The
swing at the XTAL-pins is about 1Vpp, and is
DC-compensated via an internal resistor
between the two pins. Alternatively an
external crystal oscillator could directly drive
into XTALi.
An internal switch, hardware controlled by
CDIR at pin 36, selects whether the IC
provides or receives clock signals LLC and
CREF (see Table 1). If CDIR is low, clock is
taken from the internal crystal oscillator and
the IC outputs LLC at pin 38 and CREF at
pin 39. If CDIR is high, LLC pin and CREF
pin are both switched to be input. The IC then
requires a double pixel clock LLC from
external circuitry at pin 38. Under certain
conditions, CREF input at pin 39 has
data-phase (timing) relevance, but it does not
have directly clock and data qualifying
function.
2.2 External Clock
In the “clock slave mode” case, i.e., if clock is
provided from external into LLC pin 38, a
CREF-like signal can optionally be applied to
pin 39, but this is not required. If the IC sees
a toggling signal, i.e., edges, at pin 39, CREF
will contribute to re-synchronization of the
internal horizontal counter (once per line) and
– by that – defines the active data phases in
the 16 bit wide YUV input data stream. If
horizontal synchronization from external via
RCV1 or RCV2 is selected, i.e., the encoder
IC is in slave mode regarding horizontal
timing, CREF defines together with the
selected horizontal reference input signal,
when the horizontal trigger counter has to
start. From there the programming parameter
HTRIG (11 bits in subaddress 6E and 6F)
defines the start of the horizontal pixel
counter, and the LSB of the parameter
HTRIG determines one of the two possible
phases of the internally effective CREF
relative to the external provided CREF. The
horizontal reference edge is defined
regarding source and polarity by the various
bits in subaddress 6Chec (see also later in
this application note: re-trigger).
If no CREF is provided to the IC, a horizontal
reference signal input is sampled direct with
LLC resolution. The phase of the internal
CREF, and expected valid data phases, are
defined by the selected horizontal reference
edge, and by the LSB of HTRIG. The
horizontal reference edge is defined
regarding source and polarity by the various
bits in subaddress 6Chec (see also later in
this application note: re-trigger).
Table 1. Selection of Clock Modes
CDIR
LLC
CREF
XTALo
XTALi
Pin 36 Pin 38
Pin 39
Pin 40
Pin 41
low output
output
local crystal
low output
output
don’t care
external
oscillator
high
input
don’t care
but constant
don’t care
high input
input
don’t care
high
input from don’t care
DMSD/CGC but constant
don’t care
high
input from input from
DMSD/CGC DMSD/CGC
don’t care
RTCI
RTCE
Pin 43
subaddress
61hex
don’t care don’t care
don’t care don’t care
don’t care
don’t care
RTCO from
DMSD
RTCO from
DMSD
0
0
1
1
May 1994
1
1 page  
Philips Semiconductors
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
3.1.3 Pin 6 as Output: RCV1
Pin 6 RCV1 can assume output as well as
input function and carries field synchronizing
raster control information. Via two SRCV1x
bits, PRCV1 bit and ORCV1 bit in
subaddress 6Chex one of three types of field
sync signals can be determined for RCV1
output.
Table 3. Selection of RCV1 output signal function on pin 6
F = relevant function, x = other function/signal definition, – = don’t care
BITS UNDER
SUBADDRESS 6Ch
BITS UNDER
SUBADDRESS 61h
SHORT NAME
FUNCTION
RESULTING SIGNAL
76543210 76543210
–x x x x x xF
FISE
select field frequency (V-pulse sequence)
select number of clocks/line (defines FSEQ as 4 or 8 field se-
quence)
xxxxFxxx
PRCV1
Select RCV1 signal polarity
xxxFxxxx
ORCV1
Input or Output of RCV1 signal
FF x x x x x x
SRCV1
Select RCV1 signal function
xx 0x
– input
RCV1 is input, see Table 6
00 10
0 VS 50Hz
Active high for 2.5 lines at begin of every field
00 11
0 VS 50Hz
Active low for 2.5 lines at begin of every field
00 10
1 VS 60Hz
Active high for 3 lines at begin of every field
00 11
1 VS 60Hz
Active low for 3 lines at begin of every field
01 10
0 FS 50Hz
Low in first (odd) field, 312.5 lines
High in second (even) field, 312.5 lines
01 11
0 FS 50Hz
High in first (odd) field, 312.5 lines
Low in second (even) field, 312.5 lines
01 10
1 FS 60Hz
Low in first (odd) field, 262.5 lines
High in second (even) field, 262.5 lines
01 11
1 FS 60Hz
High in first (odd) field, 262.5 lines
Low in second (even) field, 262.5 lines
10 10
0 FSEQ 50Hz
High in the first field of 8 field sequence
10 11
0 FSEQ 50Hz
Low in the first field of 8 field sequence
10 10
1 FSEQ 60Hz
High in the first field of 4 field sequence
10 11
1 FSEQ 60Hz
Low in the first field of 4 field sequence
11 ––
x n.a.
reserved, do not use
May 1994
5
5 Page 
Philips Semiconductors
Clock and synchronization signals of SAA7187 and SAA7188
Application note for digital video encoder
6.0 APPLICATION EXAMPLE
Figure 4 points out several of those features
that can be realized in an application with
SAA7188A (or SAA7187). Two or more digital
video encoder devices can be locked to each
other. All their analog video outputs are
completely in phase: horizontally, vertically
and also the subcarrier. One of the devices
functions as timing master, the other ones
work in sync slave mode. The master device
provides on RCM1 the color field sequence
indication signal FSEQ, which transports
horizontal and vertical reference as well as
subcarrier phase reference via the color field
sequence indication. The RCV1 inputs of the
other devices are set to FSEQ function and
also used to trigger line timing. VTRIG and
HTRIG are both set to zero.
RCM2 output of the master device can be
freely defined in horizontal timing. By that it
can be used as input data gating signal
(HREF–gate) at the RCV2 inputs of the other
encoder devices. This RCM2 output signal of
the master device (or of each device) could
also be fed back to its own RCV2 input for
input data gating function.
RCM1 and RCM2 outputs of the slave
devices can be used as trigger and timing
signals for the digital video signal sources.
RCM1 can be chosen as a vertical sync, or
as an odd/even signal. RCM2 can be defined
as an HS for trigger and counting purposes,
or it can be used as a source gating signal. It
can be placed ‘early’ to compensate for
pipeline delay on the data delivery side, such
as memory access, etc.
If the RCV2 pins of the slave (and/or the
master) device are not used as gating input,
they could be switched to output, and could
be used as (early) enabling signal (CBN) at
the signal source. In that case even VBI
blanking is supported. (This option is not
shown in Figure 4).
The digital encoder that works as timing
master in the configuration of Figure 4 can be
genlocked to an analog video reference
signal via digital encoder circuitry. For this
purpose, the SAA7188A can be combined
with the SAA7151B, SAA7157 and
TDA8708/09. The SAA7187 can be
combined with the SAA7191B, SAA7197 and
TDA8708/09 or with the SAA7110. The digital
real-time decoder system locks itself to the
analog reference video signal and generates
line-locked clock, horizontal and vertical sync
signals, and the real-time control signal RTC.
If the encoder runs with the line-locked clock
of the decoder, it is important to also have the
RTC wire connected, in order to maintain the
correct subcarrier frequency in the encoder,
same as in the analog reference signal. To
have the same clock at both the decoder and
encoder side is very interesting in some
applications; for example, as a frame buffer
as it avoids the complications of an
asynchronous two-clock system.
The SAA7151B or other decoder can provide
a pair of vertical and horizontal syncs as VS
and HS, or provide an odd/even signal FS
(“ODD” on pin 39 of SAA7151B, for example)
to synchronize the digital encoder to the
reference video signal, and also into the
correct interlace sequence. Proper
programming of HTRIG and VTRIG can
adjust pipeline processing delay in decoder
and/or frame buffer circuitry. If FS from the
decoder is used as RCV1 input for the first
“master” encoder, it can also be utilized as a
horizontal reference signal. Then RCV2 is
free to be used as gating input, fed by the
RCM2 output, or it can be switched to output
a CBN-like signal to one of the video signal
sources.
Figure 4 shows a rather complex system,
but the various timing techniques, as
discussed above, can be applied in simpler
systems, too.
May 1994
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AN7187.PDF ] | |
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