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PDF CX28344 Data sheet ( Hoja de datos )
| Número de pieza | CX28344 | |
| Descripción | (CX2834x) Dual / Triple / Quad / Hex / Octal - Enhanced DS3 / E3 Framer | |
| Fabricantes | Conexant | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CX28344 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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CX28342/3/4/6/8
Dual/Triple/Quad/Hex/Octal-Enhanced
Distinguishing Features
DS3/E3 Framer
! Two, three, four, six, eight independent T3/
The CX28342/3/4/6/8 provides Dual, Triple, Quad, Hex, and Octal DS3/E3 E3 framers in one package
framers designed to support DS3-M13, DS3-C-bit parity, E3-G.751, and
E3-G.832 transmission formats.
! Line coding supported:
" T3-B3ZS, NRZ, AMI
" E3-HDB3, NRZ, AMI
The CX28342/3/4/6/8 provides framing recovery for M13, M23, C-bit ! Framing supported:
parity, G.751, and G.832 formatted signals. A FIFO buffer in the receive
" T3-M13, M23, C-bit parity
path can be enabled to reduce jitter on the incoming data. The CX28342/ " E3-G.751, G.832
3/4/6/8 devices allow for ease of configuration, while providing
! Inserts and extracts overhead bits
maximum flexibility to support the transmission and recovery of industry ! Full FEAC and TDL channels support
standard formats. It provides a flexible overhead bit generation method in ! Full Performance Monitoring support per
DS3/E3 modes to source overhead bits on an individual framer.
T1.231
! Integrated Dejitter FIFO
NOTE:
The index letter i, appearing in a register’s name, represents the
channel number, one per channel.
! Glueless interfaces to the following
processors:
" Intel: 8051, 8151, 8031, 8751, 8x251
" Motorola: 68000, 68020, 68030, 68302
! An asynchronous processor interface
Functional Block Diagram
VCO
RXCKI
! LIU Interfaces:
" Glueless interface to Conexant’s DS3/E3
LIU (CX2832/3)
" Option for a definition of LIU’s clocks
polarity-sampling edge
RXPOS
RXDAT
RXNEG
RXMSY
LINECK
RXGAPCK
TXPOS
REXTCK
TXNEG
Channel 1
TXDATI
TCLKO
Framer
TXCKI
(Typical All Channels) TEXT
TEXTCK
TXSY
TXGAPCK
! Power Supplies and Power Consumption
" I/O 3.3 V, input 5 V-tolerant, core 2.5 V
" Requires 3.3 V and 2.5 V power
supplies. Optional 5 V supply required
for 5 V input tolerance
" Low power operation (<200 mW per
port)
Applications
Channel 2
Framer
Channel 3
Framer
ONESEC
MOTO
AD
A
ALE
RD
WR
CS
DTACK
INTR
! Digital Cross-Connect Systems
! Digital PCM Switches
! Access Concentrators
! CSUs
! ATM Switches
! Concentrators
! PBXs
! Routers
! Test Equipment
Testing
! JTAG boundary scan support
Channel 4
Framer
28348-DSH-001-B
Mindspeed Technologies™
February
2003
1 page  
CX28342/3/4/6/8 Data Sheet
Contents
3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
General1 Control Register (GCR00)
3-7
General2 Control Register (GCR01)
3-8
Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Mode Control Register (CR00i)
Counter Interrupt Control Register (CR01i)
3-9
3-10
Dual-Edge Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Alarm Start Interrupt Control Register (CR02i)
3-11
Alarm End Interrupt Control Register (CR03i)
3-12
3.4 Feature Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Feature1 Control Register (CR04i)
3-13
Feature2 Control Register (CR05i)
3-14
Feature3 Control Register (CR06i)
3-15
Feature4 Control Register (CR07i)
Feature5 Control Register (CR08i)
3-16
3-17
Transmit Overhead Insertion Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Transmit Overhead Insertion1 Control Register (CR09i)
3-19
DS3-C Bit Parity
3-20
REXTCK Control Register (CR11i)
3-22
Receive Overhead Control Register (CR12i)
3-23
Transmit Data Link Control Register (CR13i)
3-24
Transmit Data Link Threshold Control Register (CR14i)
3-24
Transmit Data Link Message Byte (CR15i)
3-25
Receive Data Link Control Register (CR16i)
3-25
Receive Data Link Threshold Control Register (CR17i)
3-26
Transmit FEAC Channel Byte (CR18i)
3-26
Error Insertion Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
Error Insertion1 Control Register (CR19i)
3-27
Error Insertion2 Control Register (CR20i)
3-28
3.5 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Source Channel Status Register (GSR00)
3-29
Part Number/Hardware Version Register (GSR01)
3-30
Channel Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
DS3/E3 Maintenance Status Register (SR00i)
Interrupt Source Status Register (SR01i)
3-31
3-32
Counter Interrupt Status Register (SR02i)
3-33
Dual-Edge Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
Alarm Start Interrupt Status Register (SR03i)
3-34
Alarm End Interrupt Status Register (SR04i)
3-35
E3-832 MA Fields Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
E3-G.832 MA Fields Status Register (SR06i)
3-36
E3-G.832 SSM Field Status Register (SR07i)
3-36
Transmit Data Link FEAC Status Register (SR08i)
3-37
Receive Data Link Status Register (SR11i)
3-38
Receive Data Link Message Byte (SR12i)
Receive FEAC Status Register (SR17i)
3-39
3-41
Receive AIC Byte (SR18i)
3-41
28348-DSH-001-B
Mindspeed Technologies™
v
5 Page 
1.0 Product Description
1.1
Overview
The CX28342/3/4/6/8 device includes two, three, four, six, and eight identical framers
that perform the following functions:
! Signal encoding and decoding
! Frame synchronization and recovery
! Alarm detection and generation
! Far End Alarm Control (FEAC) processing
! Data link processing
! Error and event counting
! Signal and frame generation
Each framer in the CX28342/CX28343/CX28344/CX28346/CX28348 device can be
configured individually and is capable of operating at 44.736 Mbps in DS3 mode and
34.368 Mbps in E3 mode. Each framer is composed of a transmitter block and a receiver
block. In addition, the CX28342/3/4/6/8 framer includes a microprocessor interface.
Data into the receiver can be in B3ZS/HDB3, AMI, or NRZ format. The B3ZS/HDB3
or AMI data is decoded and the bipolar input is converted to unipolar. The data can then
be applied to a First In First Out (FIFO) buffer to reduce jitter on the incoming data. The
FIFO buffer provides a Voltage Controlled Oscillator (VCO) control signal to an
external clock recovery circuit. A dejittered clock (RXCKI) from the VCO can then be
used to read data from the FIFO buffer going to the remaining receiver circuitry.
Each of the receiver blocks provides framing recovery for the M13/M23 DS3, C-bit
Parity DS3, E3-G.751, and E3-G.832 formatted signals. The data bits are extracted
from the received frame and transferred serially to the system. The transmitter can
process serial data from an external pin. In addition, the transmitter can generate AIS/
RAI/RDI and IDLE code. The transmitter also transmits the Link Access Direct
(LAPD) data link data in HDLC format. The HDLC data is transmitted through a 128-
byte FIFO buffer. The microprocessor can use the FIFO status for data transfer. The
transmitter can transmit the FEAC channel data in several modes.
The microprocessor interface supports the Intel and Motorola microprocessors. The
microprocessor is responsible for configuration, control, and monitoring of the
framer. The framers have various event detectors, status indicators, and counters,
which are readable by the microprocessor. The microprocessor interface includes
(depending on the device) one (CX28342/3/4) or two (CX28346/8) interrupt pins that
combine several sources of individually masked interrupts (i.e. the start and end of
events, OOF, IDLE, AIS, and RAI/RDI). Status indicators that are available to the
microprocessor through status registers are start of a Severely Errored Framing Event
(SEF), Yellow Alarm (RAI, RDI), Alarm Indication Signal (AIS), Idle, Out of Frame
(OOF), and Loss of Signal (LOS).
28348-DSH-001-B
Mindspeed Technologies™
1-1
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet CX28344.PDF ] | |
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