PDF SPHE8200A Data sheet ( Hoja de datos )

Número de pieza	SPHE8200A
Descripción	DVD Single Chip MPEG AV Processor
Fabricantes	Sunplus
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No Preview Available ! www.DataSheet4U.com FoSruSn&UplNuMDSPsNrVEPoDICcHRCeSsoEiCnsTn8ogUHrl2fEei0SdACC0hEeNAiHpnDOMNtiPIaNOESlGLELAYO/VINGCY Preliminary OCT. 07, 2003 Version 0.2 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. 1 page www.DataSheet4U.com Preliminary SPHE8200A 2.FEATURE Single Chip Integrated DVD Servo and A/V Decoder — Support up to 4 SDRAM devices Integrated DVD/CD Servo Controller — Support 16M/64M/128M/256M SDRAM devices — Support 1x ~ 2x DVD format reading — Support 1x ~ 16x CD format reading Embedded 32-bit RISC Processor without external host l Ycontroller tiaEmbedded Audio Processor supports multiple audio standards GEmbedded I/O processor supports programmable interface n Ocontrol Embedded TV encoder with multi-channel built-in high-speed e Lvideo DAC supports various display standards fid O CEmbedded audio ADC supports stereo analog audio input n N INBuilt-in system PLL and audio PLL generate all clock sources required from single 27MHz input Support following disc format: o H E— DVD Navigation 1.0 C C— DVD audio s E IS— SVCD (Chaoji VCD) — OKO disc lu T D— VCD 2.0/1.1/1.0 Y— CDDA / HDCD np IC N L— CDROM (game, WMA and JPEG disc) A NCSS/CPPM hardware — Built-in CSS hardware u N H O— Built-in CPPM C2_DCBC and C2_D/C2_D function S N CVideo Decoder U R E— Real time MPEG2 MP@ML decoding — Real time MPEG1 D1 (720x480x30 /720x576x25) decoding S E S— Hardware accelerated JPEG decoding or M U— Advanced decoding and display control Sub-picture Decoder — Advanced Sub-Picture Decoder for DVD SVCD and OKO F &— Support hardware vertical scaling Graphics — Embedded 2D Graphics Accelerator — BitBlt, line, triangle drawing support Display — De-interlacing of interlaced video source — Flexible vertical interpolation — Flexible horizontal interpolation with optional CIF filter — Powerful cropping and panning effect — Support YUV422, 8-bit indexed color or 16-bit direct color format OSD — Multiple OSD regions with different formats — Support 4/16/256 indexed color — Support 16/24-bit direct color — Support x2/x3/x4 horizontal scaling Embedded TV encoder — Simultaneous multi-channel output — Support 480i/480p/576i/576p format — Support 640x480 VGA / 800x600 SVGA format — Support CVBS output — Support SVideo, Component (YUV / YPbPr) or RGB output — Macrovision 7.01 and Macrovision AGC v1.03 copy protection Interface — 27MHz crystal driver — 16/32-bit SDRAM interface — 8/16-bit ROM/FLASH/SRAM interface — UART ports — IR and VFD support — Video DAC analog output — Simultaneous 10-channel audio DAC output Audio Decoder — IEC958/SPDIF digital input / output — Flexible Programmable DSP Architecture — Analog audio input — Embedded high resolution audio quality ADC — External ADC digital input interface (optional) — Support CDDA, HDCD, and DVD-Audio — Optional ATAPI and I2S interface support — Support LPCM, PCM, and WMA playback — Optional Parallel Port interface support — Support MPEGI/II layer 1/2 and MPEG 2.5 playback (with Low power optional down-mixing) — Advanced low power design — Support Dolby Digital AC3 5.1ch / DTS 5.1ch playback (with — Selective standby mode optional down-mixing) — Programmable low speed operation — Support Key Shift of 2 channels Technology — Support equalization, reverb and special sound field — Advanced CMOS technology SDRAM controller — 216pin LQFP package — High Performance SDRAM controller — 3v (I/O) and 1.8v (kernel) power supplies — Support 16 or 32 bit operation — 5v I/O tolerance © Sunplus Technology Co., Ltd. Proprietary & Confidential 5 OCT. 07, 2003 Preliminary Version: 0.2 5 Page www.DataSheet4U.com Preliminary SPHE8200A Signal R_CS1_B/GPIO Pin State Description 69 I/O ROM / SRAM / flash chip select #1 (first device) or GPIO tial GYR_CS2_B/GPIO nfidenNOLOINCR_CS3_B/GPIO nplus ICCoTEACNHDINSLEYCLKIN u N HCLKOUT S N C OM_DD[7] U R EM_DD[6] S E SM_DD[5] M_DD[4] or M UM_DD[3] M_DD[2] F &M_DD[1] Priority selection sft_cfg1[0]=1’b1 (other) Function R_CS1_B (default) GPIO[13] 70 I/O ROM / SRAM / flash chip select #2 or GPIO Priority selection sft_cfg1[1]=1’b1 sft_cfg4[8:6]=3’b100 (other) Function R_CS2_B (default) DSP FL2 GPIO[35] 71 I/O ROM / SRAM / flash chip select #3 or GPIO Priority selection sft_cfg1[2]=1’b1 sft_cfg4[11:9]=3’b100 (other) Function R_CS3_B (default) DSP FLAGOUT GPIO[36] Crystal / Clock Pins (2) 78 I Clock input / crystal in (XTALI) 77 O Clock output / crystal out (XTALO) SDRAM Interface Pins (57) 80 I/O SDRAM data bus [7] 81 I/O SDRAM data bus [6] 82 I/O SDRAM data bus [5] 83 I/O SDRAM data bus [4] 84 I/O SDRAM data bus [3] 86 I/O SDRAM data bus [2] 87 I/O SDRAM data bus [1] M_DD[0] 88 I/O SDRAM data bus [0] M_WE_B 89 O SDRAM write enable / row precharge M_CAS_B 91 O SDRAM column address strobe M_RAS_B 92 O SDRAM row address strobe / precharge M_CS_B 93 O SDRAM chip select M_BA0 94 O SDRAM bank select address [0] M_DD[15] 96 I/O SDRAM data bus [15] M_DD[14] 97 I/O SDRAM data bus [14] M_DD[13] 98 I/O SDRAM data bus [13] M_DD[12] 99 I/O SDRAM data bus [12] M_DD[11] 101 I/O SDRAM data bus [11] © Sunplus Technology Co., Ltd. Proprietary & Confidential 11 OCT. 07, 2003 Preliminary Version: 0.2 11 Page

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