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PDF SP5668KGMP1S Data sheet ( Hoja de datos )
| Número de pieza | SP5668KGMP1S | |
| Descripción | 2.7GHz 3-Wire Bus Controlled Synthesiser | |
| Fabricantes | Mitel Networks | |
| Logotipo |  |
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SP5668
2.7GHz 3-Wire Bus Controlled Synthesiser
Preliminary Information
DS4538 - 1.6 January 1997
.
The SP5668 is a single chip frequency synthesiser
designed for tuning systems up to 2.7GHz.
The RF preamplifer contains a divide by two prescaler
which can be disabled for applications up to 2GHz so enabling
a step size equal to the comparison frequency up to 2GHz and
twice the comparison frequency up to 2.7GHz.
Comparison frequencies are obtained either from a crystal
controlled on–chip oscillator or from an external source.
The device contains three switching ports, P0 – P2,
together with an ’in–lock’ flag output. Various test modes
including varactor disable and charge pump disable are also
included.
FEATURES
s Complete 2.7GHz single chip system
s Optimised for low phase noise
s Selectable divide by two prescaler
s Selectable reference division ratio
s Charge pump disable
s Varactor line disable
s ‘In–lock’ flag
s Two selectable charge pump currents
s Three switching ports
s Reference frequency output
s ESD protection (Normal ESD handling procedures
should be observed)
CHARGE PUMP
CAP Q1
CRYSTAL Q2
ENABLE
DATA
CLOCK
PORT P2
PORT P1/OC
DRIVE
VEE
RF INPUT
RF INPUT
VCC
LOCK
REF
PORT P0/OC
Fig. 1 Pin connections - top view
MP16
APPLICATIONS
s SAT, TV, VCR and Cable tuning systems
s Communications systems
ORDERING INFORMATION
SP5668/KG/MP1S (Tubes,)
SP5668/KG/MP1T Tape and Reel)
1 page  
SP5668
PHASE NOISE
The SP5668 has been designed to offer good phase noise
performance even when operated with a standard low profile
4MHz crystal and a high comparison frequency, e.g. 2MHz.
The typical phase noise performance measured in the
standard application is contained in Table 4. It has been
demonstrated that even higher levels of performance will be
achieved in a tuner application.
TEST MODES
The programmable divider output divided by two Fpd/2 and
the comparison frequency Fcomp, can be switched to ports P0
and P1 respectively.
The charge pump can be forced to either source or sink
current, and may be disabled to high impedance state.
The varactor DRIVE output can be disabled by the OS bit
within the data word, so switching the external transistor 'OFF'
and allowing an external voltage to be written to the varactor
line for tuner alignment purposes.
The test modes are described in Table 2.
CLOCK
ENABLE
DATA MSB
2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16
2 0 LSB
P2 P1 P0 TO OS CO R2 R1 R0 PE
FREQUENCY DATA
216 to 20
PE
R2 , R1 , R0
P2, P1, P0
CO
OS
T0
t : Programmable divider ratio control bits
: ÷2 Prescaler (Enable = 1, Disable = 0)
t : Reference divider ratio control bits (see Table 1)
t : Port control bits
t : Charge Pump current select (see Table 3)
t : Drive output disable switch
t : Test mode enable (see Table 2)
R2 R1
00
00
01
01
10
10
11
11
P1
X
0
0
1
1
X = Don't care
P0
X
0
1
0
1
Fig. 3 Data format and timing
R0
RATIO
Comparison Frequency with a 4MHz
external reference
02
2MHz
14
1MHz
08
500kHz
1 16
250kHz
0 32
125kHz
1 64
62.5kHz
0 128
31.25kHz
1 256
15.625kHz
Table 1 Reference division ratio
T0 FUNCTIONAL DESCRIPTION
0 Normal operation
1 Charge pump sink. LOCK output = Lo Z
1 Charge pump source. LOCK output = Hi Z
1 Charge pump disable. LOCK output = Lo Z
1 Port P1 = Fcomp: Port 0 = Fpd/2
Table 2 Test modes
5
5 Page 
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet SP5668KGMP1S.PDF ] | |
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