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PDF 2K30A Data sheet ( Hoja de datos )
| Número de pieza | 2K30A | |
| Descripción | DSP56301 Digital Signal Processor | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
Chip Errata
DSP56301 Digital Signal Processor
Mask: 2K30A
General remark: In order to prevent the use of instructions or sequences of instructions that
do not operate correctly, we encourage you to use the “lint563” program to identify such
cases and use alternative sequences of instructions. This program is available as part of the
Motorola DSP Tools CLAS package.
Silicon Errata
Errata
Number
Errata Description
Description (added 8/16/2001):
Applies
to Mask
2K30A
ES133
Some K30A devices shipped under an XC part number are subject to a problem
if operated in DMA mode 5. The problem occurs if two consecutive host
commands are sent to the DSP. The second host command is received, the
corresponding answer message is composed, and the DMA channel is set up
correctly to transmit the message to the host. However, the message is never sent.
The host port status register shows a host transmit data request (bit HTRQ in
HSTR is set.) DTDn is never set, indicating there has been no terminated
transfer. Sequences of: 1. data, 2. host command to terminate the transfer, and
3. acknowledgement from the host work properly and can be repeated as often
as needed. If a second host command is sent to the DSP, without first sending
data, the DMA channel locks up. This problem has proven to be low level to
date, occurring at a rate of about 350 ppm. The product’s performance regarding
this issue does not drift over time; that is, it is not a reliability risk.
The problem can also be manifested in other modes when more than one DMA
channel is operating, with two or more channels moving data while one is
servicing the PCI FIFO. In this case, the channel servicing the PCI FIFO stalls
and the PCI bus enters an endless state of retries.
Motorola Semiconductor Products Sector
301CE2K30A_0_8
6501 William Cannon Drive WeFsot,rAMusotirne, TIenxfaosrm7a87ti3o5n-8O59n8 This Product,
Go to: www.freescale.com
ng 12/19/02 pg. 1
1996-2002 Motorola
1 page  
Errata
Number
ED13
ED15
ED17
ED18
ED19
Freescale Semiconductor, Inc.
Chip Errata
DSP56301 Digital Signal Processor
Mask:2K30A
Document Update
Applies
to Mask
Description (added 5/15/98):
2K30A
When the HI32 is in PCI mode, the Insert Address Enable control
bit (IAE=1) can be set only with the Receive Buffer Lock Enable
control bit set (RBLE=1 in the DPCR register.)
Description (added 7/21/98):
2K30A
The DRAM Control Register (DCR) should not be changed while
refresh is enabled. If refresh is enabled only a write operation that
disables refresh is allowed.
Workaround:
First disable refresh by clearing the BREN bit, than change other
bits in the DCR register, and finally enable refresh by setting the
BREN bit.
Description (added 9/28/98):
2K30A
In all DSP563xx technical datasheets, a note is to be added under
"AC Electrical Characteristics" that although the minimum value
for "Frequency of Extal" is 0MHz, the device AC test conditions are
15MHz and rated speed.
Workaround:
N/A
Description (added 11/2/98):
2K30A
The PCI host must not change the values of the HBE[3:0] bits
during PCI read transactions from the HI32 as a PCI target.
Description (added 11/9/98):
2K30A
To guarantee the proper HI32 operation, the DMA should service
the HI32 under the following restrictions:
• Two DMA channels should not service the DRXR FIFO if
master and slave data is mixed there.
• The DMA data transfers should not be concurrent with the
56300 Core data transfers to/from the same HI32 data
FIFO.
DSP56301 Errata
1996-2002, Motorola
For Mor3e01ICnEfo2rKm30aAti_o0n_8On This Product,
Go to: www.freescale.com
ng 12/19/02 pg. 5
5 Page 
Freescale Semiconductor, Inc.
Chip Errata
DSP56301 Digital Signal Processor
Mask:2K30A
Errata
Number
ED33
Document Update
Applies
to Mask
Description (added 12/16/98; identified as a Documentation errata
2/1/99):
2K30A
When Stack Extension mode is enabled, a use of the instructions BRKcc
or ENDDO inside do loops might cause an improper operation.
If the loop is non nested and has no nested loop inside it, the erratais
relevant only if LA or LC values are being used outside the loop.
Workaround:
If Stack Extension is used, emulate the BRKcc or ENDDO as in the
following examples. We split between two cases, finite loops and do
forever loops.
1) Finite DO loops (i.e. not DO FOREVER loops)
==============================================
BRKcc
Original code:
do #N,label1
.....
.....
do #M,label2
.....
.....
BRKcc
.....
.....
label2
.....
.....
label1
Will be replaced by:
do #N, label1
.....
.....
do #M, label2
.....
.....
Jcc fix_brk_routine
.....
.....
DSP56301 Errata
1996-2002, Motorola
For Mor3e01ICnEfo2rKm30aAti_o0n_8On This Product,
Go to: www.freescale.com
ng 12/19/02 pg. 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet 2K30A.PDF ] | |
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