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PDF LTC1274 Data sheet ( Hoja de datos )
| Número de pieza | LTC1274 | |
| Descripción | 12-Bit/ 10mW/ 100ksps ADCs with 1uA Shutdown | |
| Fabricantes | Linear Technology | |
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LTC1274/LTC1277
12-Bit, 10mW, 100ksps
ADCs with 1µA Shutdown
FEATURES
s Low Power Dissipation: 10mW
s Sample Rate: 100ksps
s Samples Inputs Beyond Nyquist, 72dB S/(N + D)
and 82dB THD at fIN = 100kHz
s Single Supply 5V or ±5V Operation
s Power Shutdown to 1µA in Sleep Mode
s 180µA Nap Mode (LTC1277) with Instant Wake-Up
s Internal Reference Can Be Overdriven
s Internal Synchronized Clock
s 0V to 4.096V or ±2.048V Input Ranges (1mV/LSB)
s 24-Lead SO Package
APPLICATI S
s Battery-Powered Portable Systems
s High Speed Data Acquisition for PCs
s Digital Signal Processing
s Multiplexed Data Acquisition Systems
s Audio and Telecom Processing
s Spectrum Analysis
DESCRIPTIO
The LTC®1274/LTC1277 are 8µs sampling 12-bit A/D
converters which draw only 2mA (typ) from single 5V or
±5V supplies. These easy-to-use devices come complete
with a 2µs sample-and-hold, a precision reference and an
internally trimmed clock. Unipolar and bipolar conversion
modes add to the flexibility of the ADCs.
Two power-down modes are available in the LTC1277. In
Nap mode, the LTC1277 draws only 180µA and the instant
wake-up from Nap mode allows the LTC1277 to be pow-
ered down even during brief inactive periods. In Sleep
mode only 1µA will be drawn. A REFRDY signal is used to
show the ADC is ready to sample after waking up from
Sleep mode. The LTC1274 also provides the Sleep mode
and REFRDY signal.
The A/D converters convert 0V to 4.096V unipolar inputs
from a single 5V supply or ±2.048V bipolar inputs from
±5V supplies.
The LTC1274 has a single-ended input and a 12-bit
parallel data format. The LTC1277 offers a differential
input and a 2-byte read format. The bipolar mode is
formatted as 2’s complement for the LTC1274 and offset
binary for the LTC1277.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATI
Single 5V Supply, 10mW, 100kHz, 12-Bit ADC
2.42V
VREF OUTPUT
ANALOG
DIFFERENTIAL INPUTS
(0V TO 4.096V)
+
10µF
0.1µF
1
2
3
4
5
6
7
8
9
10
8-BIT
PARALLEL
BUS
11
12
LTC1277
AIN+
AIN–
VREF
AGND
REFRDY
VDD
VSS
BUSY
CS
RD
SLEEP
NAP
D7
D6
D5
D4
CONVST
HBEN
VLOGIC
D0/8
D1/9
D2/10
DGND
D3/11
24
23
22
21
20
19
18
17
16
15
14
13
+
10µF
µP
CONTROL
LINES
5V
0.1µF
OPTIONAL 3V SUPPLY
TO INTERFACE WITH 3V
PROCESSOR
LTC1274/77 • TA01
Supply Current vs Sample Rate with
Sleep and Nap Modes
10000
CREF = 4.7µF
WITHOUT SLEEP OR NAP
1000
NAP MODE
100
10
1
0.1
NAP = REFRDY
(SLEEP MODE)
NAP = 5V
(SLEEP MODE)
1 10 100 1k 10k 100k
SAMPLE RATE (Hz)
LTC1274/77 • TA02
1
1 page  
WU
TI I G CHARACTERISTICS (Note 5) See Figures 13 to 17.
LTC1274/LTC1277
SYMBOL
t16
t17
t18
PARAMETER
HBEN↓ to Low Byte Data Valid
HBEN↑ to RD↓ Setup Time
RD↑ to HBEN↓ Setup Time
CONDITIONS
CL = 100pF (LTC1277 Only)
(Note 10) (LTC1277 Only)
(Note 10) (LTC1277 Only)
MIN TYP MAX UNITS
q
45 100
ns
q 10
ns
q 10
ns
The q denotes specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together and VLOGIC is tied to VDD in LTC1277 (unless
otherwise noted).
Note 3: When these pin voltages are taken below VSS (ground for unipolar
mode) or above VDD, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA below VSS (ground for
unipolar mode) or above VDD without latch-up.
Note 4: When these pin voltages are taken below VSS (ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below VSS (ground for unipolar mode)
without latch-up. These pins are not clamped to VDD.
Note 5: VDD = 5V (VSS = – 5V for bipolar mode), VLOGIC = VDD (LTC1277),
fSAMPLE = 100ksps, tr = tf = 5ns unless otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: For LTC1274, bipolar offset is the offset voltage measured from
– 0.5LSB when the output code flickers between 0000 0000 0000 and
1111 1111 1111. For LTC1277, bipolar offset voltage is measured from
– 0.5LSB when the output code flickers between 0111 1111 1111 and
1000 0000 0000.
Note 9: The AC tests apply to bipolar mode only and the S/(N + D) is 71dB
(typ) for unipolar mode at 100kHz input frequency.
Note 10: Guaranteed by design, not subject to test.
Note 11: Recommended operating conditions.
Note 12: AIN must not exceed VDD or fall below VSS by more than 50mV to
specified accuracy.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 400ns after conversion start (i.e., before the first bit decision) or
after BUSY rises (i.e., after the last bit test). See timing diagrams Modes
1a and 1b (Figures 13, 14).
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs
Output Code
1.00
fSAMPLE = 100kHz
0.50
0
–0.50
–1.00
0 512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
LT1274/77 • TPC01
Differential Nonlinearity vs
Output Code
1.00
fSAMPLE = 100kHz
0.50
0
–0.50
–1.00
0 512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
LT1274/77 • TPC02
ENOBs and S/(N + D) vs
Input Frequency
12
11
10 NYQUIST
9 FREQUENCY
8
7
6
5
4
3
2
1 fSAMPLE = 100kHz
0
10k 100k
INPUT FREQUENCY (Hz)
74
68
62
56
50
1M 2M
LTC1274/77 • TPC03
5
5 Page 
LTC1274/LTC1277
APPLICATIONS INFORMATION
using an FFT algorithm, the ADCs’ spectral content can be
examined for frequencies outside the fundamental. Figures
2a and 2b show typical LTC1274 FFT plots.
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the A/D output. The output is band
limited to frequencies above DC and below half the sam-
pling frequency. Figure 2a shows a typical spectral content
with a 100kHz sampling rate and a 48.85kHz input. The
dynamic performance is excellent for input frequencies well
beyond Nyquist as shown in Figure 2b and Figure 3.
0
fSAMPLE = 100kHz
–20 fIN = 48.85kHz
12 74
11 68
10
NYQUIST
62
9
FREQUENCY
56
8 50
7
6
5
4
3
2
1 fSAMPLE = 100kHz
0
10k 100k
INPUT FREQUENCY (Hz)
1M 2M
LTC1274/77 • F03
Figure 3. ENOBs and S/(N + D) vs Input Frequency
–40
–60
–80
–100
–120
0
10 20 30 40
INPUT FREQUENCY (kHz)
50
LTC1274/77 • F02a
Figure 2a. LTC1274 Nonaveraged, 4096 Point
FFT Plot with 50kHz Input Frequency
0
fSAMPLE = 100kHz
–20 fIN = 97.68kHz
–40
–60
–80
–100
–120
0
10 20 30 40
INPUT FREQUENCY (kHz)
50
LTC1274/77 • F02b
Figure 2b. LTC1274 Nonaveraged, 4096 Point
FFT Plot with 100kHz Input Frequency
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 100kHz, the LTC1274/LTC1277 maintain very
good ENOBs over 300kHz. Refer to Figure 3.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamen-
tal itself. The out-of-band harmonics alias into the
frequency band between DC and half the sampling
frequency. THD is expressed as:
THD
=
20log√V22
+
V32
+ V42
V1
...
+
VN2
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
second through Nth harmonics. THD versus input fre-
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC1274.PDF ] | |
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