NS32491 PDF Datasheet

Спецификация NS32491 изготовлена ​​​​«National» и имеет функцию, называемую «Serial Network Interface». На этой странице представлена ​​подробная информация о характеристиках и технических характеристиках детали. Если вы правильно понимаете эти части, они могут помочь вам завершить ваши проекты и отремонтировать детали.

Детали детали

Номер произв NS32491
Описание Serial Network Interface
Производители National
логотип National логотип 

10 Pages

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NS32491 Даташит, Описание, Даташиты
July 1986
DP8391 NS32491 Serial Network Interface
General Description
The DP8391 Serial Network Interface (SNI) provides the
Manchester data encoding and decoding functions for
IEEE 802 3 Ethernet Cheapernet type local area networks
The SNI interfaces the DP8390 Network Interface Controller
(NIC) to the Ethernet transceiver cable When transmitting
the SNI converts non-return-to-zero (NRZ) data from the
controller and clock pulses into Manchester encoding and
sends the converted data differentially to the transceiver
The opposite process occurs on the receive path where a
digital phase-locked loop decodes 10 Mbit s signals with as
much as g20 ns of jitter
The DP8391 SNI is a functionally complete Manchester en-
coder decoder including ECL like balanced driver and re-
ceivers on board crystal oscillator collision signal transla-
tor and a diagnostic loopback circuit
The SNI is part of a three chip set that implements the com-
plete IEEE compatible network node electronics as shown
below The other two chips are the DP8392 Coax Transceiv-
er Interface (CTI) and the DP8390 Network Interface Con-
troller (NIC)
Incorporated into the CTI are the transceiver collision and
jabber functions The Media Access Protocol and the buffer
management tasks are performed by the NIC There is an
isolation requirement on signal and power lines between the
CTI and the SNI This is usually accomplished by using a set
of miniature pulse transformers that come in a 16-pin plastic
DIP for signal lines Power isolation however is done by
using a DC to DC converter
Y Compatible with Ethernet II IEEE 802 3 10base5 and
10base2 (Cheapernet)
Y 10 Mb s Manchester encoding decoding with receive
clock recovery
Y Patented digital phase locked loop (DPLL) decoder re-
quires no precision external components
Y Decodes Manchester data with up to g20 ns of jitter
Y Loopback capability for diagnostics
Y Externally selectable half or full step modes of opera-
tion at transmit output
Y Squelch circuits at the receive and collision inputs re-
ject noise
Y High voltage protection at transceiver interface (16V)
Y TTL MOS compatible controller interface
Y Connects directly to the transceiver (AUI) cable
Table of Contents
1 0 System Diagram
2 0 Block Diagram
3 0 Functional Description
3 1 Oscillator
3 2 Encoder
3 3 Decoder
3 4 Collision Translator
3 5 Loopback
4 0 Connection Digram
5 0 Pin Description
6 0 Absolute Maximum Ratings
7 0 Electrical Characteristics
8 0 Switching Characteristics
9 0 Timing and Load Diagrams
10 0 Physical Dimensions
1 0 System Diagram
IEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set
C1995 National Semiconductor Corporation TL F 6758
TL F 6758 – 1
RRD-B30M115 Printed in U S A

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NS32491 Даташит, Описание, Даташиты
2 0 Block Diagram
TL F 6758 – 2
3 0 Functional Description
The SNI consists of five main logical blocks
a) the oscillator generates the 10 MHz transmit clock sig-
nal for system timing
b) the Manchester encoder and differential output driver
accepts NRZ data from the controller performs Man-
chester encoding and transmits it differentially to the
c) the Manchester decoder receives Manchester data
from the transceiver converts it to NRZ data and clock
pulses and sends them to the controller
d) the collision translator indicates to the controller the
presence of a valid 10 MHz signal at its input
e) the loopback circuitry when asserted switches encod-
ed data instead of receive input signals to the digital
phase-locked loop
The oscillator is controlled by a 20 MHz parallel resonant
crystal connected between X1 and X2 or by an external
clock on X1 The 20 MHz output of the oscillator is divided
by 2 to generate the 10 MHz transmit clock for the control-
ler The oscillator also provides internal clock signals to the
encoding and decoding circuits
Crystal Specification
Resonant frequency
20 MHz
g0 001% at 25 C
g0 005% 0 – 70 C
Parallel Resonance
The 20 MHz crystal connection to the SNI requires special
care The IEEE 802 3 standard requires a 0 01% absolute
accuracy on the transmitted signal frequency Stray capaci-
tance can shift the crystal’s frequency out of range causing
the transmitted frequency to exceed its 0 01% tolerance
The frequency marked on the crystal is usually measured
with a fixed shunt capacitance (CL) that is specified in the
crystal’s data sheet This capacitance for 20 MHz crystals is
typically 20 pF The capacitance between the X1 and X2
pins of the SNI of the PC board traces and the plated
through holes plus any stray capacitance such as the sock-
et capacitance if one is used should be estimated or mea-
sured Once the total sum of these capacitances is deter-
mined the value of additional external shunt capacitance
required can be calculated This capacitor can be a fixed
5% tolerance component The frequency accuracy should
be measured during the design phase at the transmit clock
pin (TXC) for a given pc layout Figure 2 shows the crystal
TL F 6758 – 3
CL e Load capacitance specified by the crystal’s manufacturer
CP e Total parasitic capacitance including
a) SNI input capacitance between X1 and X2 (typically 5 pF)
b) PC board traces plated through holes socket capacitances
Note 1 When using a Viking (San Jose) VXB49N5 crystal the external ca-
pacitor is not required as the CL of the crystal matches the input
capacitance of the DP8391
FIGURE 2 Crystal Connection
The encoder combines clock and data information for the
transceiver Data encoding and transmission begins with the
transmit enable input (TXE) going high As long as TXE re-

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NS32491 Даташит, Описание, Даташиты
3 0 Functional Description (Continued)
mains high transmit data (TXD) is encoded out to the trans-
mit-driver pair (TXg) The transmit enable and transmit data
inputs must meet the setup and hold time requirements with
respect to the rising edge of transmit clock Transmission
ends with the transmit enable input going low The last tran-
sition is always positive at the transmit output pair It will
occur at the center of the bit cell if the last bit is one or at
the boundary of the bit cell if the last bit is zero
The differential line driver provides ECL like signals to the
transceiver with typically 5 ns rise and fall times It can drive
up to 50 meters of twisted pair AUI Ethernet transceiver
cable These outputs are source followers which need ex-
ternal 270X pulldown resistors to ground Two different
modes full-step or half-step can be selected with SEL in-
put With SEL low transmit a is positive with respect to
transmit b in the idle state With SEL high transmit a and
transmit b are equal in the idle state providing zero differ-
ential voltage to operate with transformer coupled loads
Figures 4 5 and 6 illustrate the transmit timing
The decoder consists of a differential input circuitry and a
digital phase-locked loop to separate Manchester encoded
data stream into clock signals and NRZ data The differen-
tial input should be externally terminated if the standard
78X transceiver drop cable is used Two 39X resistors con-
nected in series and one optional common mode bypass
capacitor would accomplish this A squelch circuit at the
input rejects signals with pulse widths less than 8 ns (nega-
tive going) or with levels less than b175 mV Signals more
negative than b300 mV and with a duration greater than
30 ns are always decoded This prevents noise at the input
from falsely triggering the decoder in the absence of a valid
4 0 Connection Diagram
signal Once the input exceeds the squelch requirements
carrier sense (CRS) is asserted Receive data (RXD) and
receive clock (RXC) become available typically within 6 bit
times At this point the digital phase-locked loop has locked
to the incoming signal The DP8391 decodes a data frame
with up to g20 ns of jitter correctly
The decoder detects the end of a frame when the normal
mid-bit transition on the differential input ceases Within one
and a half bit times after the last bit carrier sense is de-as-
serted Receive clock stays active for five more bit times
before it goes low and remains low until the next frame
Figures 7 8 and 9 illustrate the receive timing
The Ethernet transceiver detects collisions on the coax ca-
ble and generates a 10 MHz signal on the transceiver cable
The SNI’s collision translator asserts the collision detect
output (COL) to the DP8390 controller when a 10 MHz sig-
nal is present at the collision inputs The controller uses this
signal to back off transmission and recycle itself The colli-
sion detect output is de-asserted within 350 ns after the 10
MHz input signal disappears
The collision differential inputs (a and b) should be termi-
nated in exactly the same way as the receive inputs The
collision input also has a squelch circuit that rejects signals
with pulse widths less than 8 ns (negative going) or with
levels less than b175 mV Figure 10 illustrates the collision
Logic high at loopback input (LBK) causes the SNI to route
serial data from the transmit data input through its encoder
returning it through the phase-locked-loop decoder to re-
ceive data output In loopback mode the transmit driver is in
idle state and the receive input circuitry is disabled
Refer to the Oscillator section
Top View
Order Number DP8391N
See NS Package Number N24C
TL F 6758 – 4

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