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8Q1024K8SRAM PDF даташит

Спецификация 8Q1024K8SRAM изготовлена ​​​​«Aeroflex Circuit Technology» и имеет функцию, называемую «high-performance 1M byte (8Mbit) CMOS static RAM».

Детали детали

Номер произв 8Q1024K8SRAM
Описание high-performance 1M byte (8Mbit) CMOS static RAM
Производители Aeroflex Circuit Technology
логотип Aeroflex Circuit Technology логотип 

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8Q1024K8SRAM Даташит, Описание, Даташиты
Standard Products
QCOTSTM UT8Q1024K8 SRAM
Data Sheet
January, 2003
FEATURES
‰ 25ns maximum (3.3 volt supply) address access time
‰ Dual cavity package contains two (2) 512K x 8 industry-
standard asynchronous SRAMs; the control architecture
allows operation as an 8-bit data width
‰ TTL compatible inputs and output levels, three-state
bidirectional data bus
‰ Typical radiation performance
- Total dose: 50krad(Si)
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = >10 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 5.0E-9
- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
‰ Packaging options:
- 44-lead bottom brazed dual CFP (BBTFP) (4.6 grams)
‰ Standard Microcircuit Drawing 5962-01532
- QML T and Q compliant part
INTRODUCTION
The QCOTSTM UT8Q1024K8 Quantified Commercial Off-the-
Shelf product is a high-performance 1M byte (8Mbit) CMOS
static RAM built with two individual 524,288 x 8 bit SRAMs
with a common output enable. Memory access and control is
provided by an active LOW chip enable (En), an active LOW
output enable (G). This device has a power-down feature that
reduces power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking one of the
chip enable (En) inputs LOW and write enable (Wn) inputs
LOW. Data on the I/O pins is then written into the location
specified on the address pins (A0 through A18). Reading from
the device is accomplished by taking one of the chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
Only one SRAM can be read or written at a time.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
A(18:0)
G
E1 W1
E0 W0
512K x 8
512K x 8
DQ(7:0)
Figure 1. UT8Q1024K8 SRAM Block Diagram
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8Q1024K8SRAM Даташит, Описание, Даташиты
NC
NC
A0
A1
A2
A3
A4
E1
DQ0
DQ1
VDD
VSS
DQ2
DQ3
W1
A5
A6
A7
A8
A9
W2
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 NC
43 E2
42 NC
41 A18
40 A17
39 A16
38 A15
37 G
36 DQ7
35 DQ6
34 VSS
33 VDD
32 DQ5
31 DQ4
30 A14
29 A13
28 A12
27 A11
26 A10
25 NC
24 NC
23 NC
Figure 2. 25ns SRAM Pinout (44)
PIN NAMES
A(18:0)
DQ(7:0)
En
Wn
G
VD D
VSS
Address
Data Input/Output
Device Enable
WriteEnable
Output Enable
Power
Ground
Notes:
1. To avoid bus contention, on the DQ(7:0) bus, only one En can be driven low
simultaneously while G is low.
DEVICE OPERATION
Each die in the UT8Q1024K8 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes IDD to rise to its active value, and decodes the 19 address
inputs to each memory die . Wn controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.
Table 1. Device Operation Truth Table
G Wn En I/O Mode Mode
X1 X
1 3-state
Standby
X 0 0 Data in Write
1
1
0 3-state
Read2
0 1 0 Data out Read
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than VIH (min) withEn and G less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQ(7:0) after
the specified tAVQV is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (tAVAV).
SRAM Read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified tETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
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8Q1024K8SRAM Даташит, Описание, Даташиты
WRITE CYCLE
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when eitherG is greater than V IH(min), or when Wn is less
than VIL(max).
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by tWLWH when the write is
initiated byWn, and by tETWH when the write is initiated byEn.
Unless the outputs have been previously placed in the high-
impedance state byG, the user must wait t WLQZ before applying
data to the eight bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by Wn, and by tETEF when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state byG,
the user must wait tWLQZ before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
The UT8Q1024K8 SRAM incorporates features which allow
operation in a limited radiation environment.
Table 2. Typical Radiation Hardness
Design Specifications1
Total Dose
50
krad(Si) nominal
Heavy Ion
Error Rate 2
<1E-8
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
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