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PDF MX93002FC Data sheet ( Hoja de datos )
| Número de pieza | MX93002FC | |
| Descripción | PCM CODEC | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX93002
FEATURES
. Built-in two single +5V power supply PCM CODECs . Support external volume control
. Support Digital Speakerphone application
. On-chip differential line driver
. Support automatic power-down function
. On-chip ALC (automatic level control)
. Support 2.048 or 1.536 MHz master clock for 8KHz . On-chip digital volume control
Frame Sync.
. Support £ g/A law and 16-bit format linear data
. On-chip differential 8Ω power amplifier
. On-chip programmable receive/transmit gain
. Support switch paths for DAM (digital answering control
machine) related applications
. Easy interface to general purpose DSP
. Support two comparators for power-low and
. Easy Read/Write of control registers by MCU
battery- low detection
. Easy interface to FAX or Cordless Phone
7. Support external L.P.F. for D/A output path . 44-pin PQFP/PLCC package
PIN CONFIGURATION
33332222222
32109876543
44444
65432143210
SSSSSSVAL LP
SSSSS VAL L P
DV P GP V RUP P G
DV P GP S RUP P G
EDKNKD XF F A
EDKNKV XF F A
34
SDATA
N
B
D
2
N
D
P
D
1
2 CCC
212
FILT
22
7
SDATA
N
B
D
2
N
D
P
D
D
2 CCC
212
FILT
39
35 SCLK
ALCC2 21 8 SCLK
1 ALCC2 38
36 DX1
ALCC1 20 9 DX1
ALCC1 37
37 DR1
ALCRC 19 10 DR1
ALCRC 36
38 DX2
PGAC1
18 11
DX2
PGAC1
35
39 DR2
AUX1 17 12 DR2
AUX1 34
40 FS
LIN 16 13 FS
LIN 33
41 MCLK
MIC 15 14 MCLK
MIC 32
42 VDD
VREF 14 15 VDD
VREF 31
43 DGND
AG 13 16 DGND
AG 30
44
PGND
V LL
P CP V BVOOAA
VBG
12 17
PGND
V LL
P CP V BV OOAA
VBG
29
V OOP ABUUV G
V OOP ABUUV G
C D M WO T A T T D N
C D MWO T A T T D N
P D P B WB T P N D D
P D P B WB T P N D D
12345678911
01
44 PINS PQFP
11222222222
89012345678
44 PINS PLCC
1 Ver 2.50 September 17, 1998
1 page  
MX93002
SYMBOL PIN PIN NBR.
DESCRIPTION
TYPE PQFP
(PLCC)
LPFC1 O (A) 24 (41) the option of the external passive L.P.F. (Low Pass Filter); if the pin is NC then will
by-pass L.P.F, where L.P.F. 3dB point : fc = 1/2£ k∗ 3KΩ (±10%)∗ CLPFC1)
LPFC2 O (A) 25 (42) the option of the external passive L.P.F. (Low Pass Filter); if the pin is NC then will
by-pass L.P.F, where L.P.F. 3dB point : fc = 1/2£ k∗ 3KΩ (±10%)∗ CLPFC2)
AUX2 I/O (A) 26 (43) as an I/O port for SWK and SWH
VR O (A) 27 (44) external speaker volume control; use a 10KΩ variable resistor
SVDD1 P (A) 28 (1) analog power supply; 5V power for SPK-DRV
SPKP O (A) 29 (2) the Non-inverting output of SPK-DRV with DA-PGA, ATT1 and ATT2; PGA from 0
to 9dB; Attenuator 1 & 2 from 0 to -45dB; see NOTE. 3
SGND P (A) 30 (3) analog power ground for SPK-DRV
SPKN O (A) 31 (4) the Inverting output of SPK-DRV with DA-PGA, ATT1 and ATT2; PGA from 0 to
9dB; Attenuator 1 & 2 from 0 to -45dB; see NOTE 3
SVDD2 P (A) 32 (5) analog power ground for SPK-DRV
SDENB I (D) 33 (6) the enable signal for serial control data; active low; for starting to Receive/Transmit
serial control data (A2~A0,D7~D0)
SDATA I/O (D) 34 (7) Bi-directional serial control data port; it is an interface for Microprocessor to
Transmit/Receive serial control data
SCLK I (D) 35 (8) serial control data clock; the clock source of serial control data; from
microprocessor
DX1 O (D) 36 (9) transmit serial data
DR1 I (D) 37 (10) receive serial data
DX2 O (D) 38 (11) transmit serial data
DR2 I (D) 39 (12) receive serial data
FS I (D) 40 (13) frame sync. input; 8KHz frame sync. Clock for the Transmit/Receive serial data
MCLK I (D) 41 (14) master clock input, if MCLK is continuously high or low then the MX93002 will get
into power down mode automatically
VDD P (D) 42 (15) digital power supply; 5V power supply for all internal digital logic
DGND P (D) 43 (16) digital power ground
PGND P (D) 44 (17) digital power ground; for internal PLL charge pump circuits
@ PIN TYPE : “ I” : Input Port; “ O” : Output Port; “ I/O” : Bi-direction Port; “ P” : Power
“ (D)” : Digital Pin; “ (A)” : Analog Pin
5
5 Page 
MX93002
2. Room Monitoring:
A. System initialization [set MIC gain (REG2 bit(3~0)), set ALC gain 0/+6dB (REG5 bit(1)), set LIN-DRV
gain (REG1 bit(3~0)), set REG3 bit(6,5) and set REG6 bit(1,0)]
B. Switches path:
a. Remote Monitoring:
MIC ⇒ SWA ⇒ PRE-PGA ⇒ SWC (ALC on) ⇒ SWJ ⇒ LIN-DRV ⇒ LOUTP/N
b. Local Detecting DTMF:
LIN ⇒ SWI ⇒ AD1-PGA ⇒ PCM CODEC AIN1
3. Digital Speakerphone:
A. System Initialization [set MIC gain (REG2 bit(3~0)), set AD1-PGA gain (REG6 bit(1,0)), fix the value of
L.P.F., set DA-PGA gain (REG6 bit(3,2)), set ATT1 gain (REG3 bit(3~0)), set LIN
gain (REG1 bit(7~4)), set SWM REG4 bit(4), set LIN-DRV gain (REG1 bit(3~0))]
B. Switches path : set REG0 = 0X00AF
a. CODEC 1 : Record signal from MIC and Play signal to SPKP/N (use digital volume control)
MIC ⇒ SWA ⇒ PRE-PGA ⇒ SWC (ALC off) ⇒ SWD ⇒ AD1-PGA ⇒ PCM CODEC AIN1
PCM CODEC AOUT1 ⇒ L.P.F. ⇒ SWF ⇒ SWG (ATT1) ⇒ SPK-DRV ⇒ SPKP/N
b. CODEC 2 : Record signal from LIN and Play signal to LOUTP/N
LIN ⇒ SWM ⇒ AD2-PGA ⇒ PCM CODEC AIN2
PCM CODEC AOUT2 ⇒ SWE ⇒ LIN-DRV ⇒ LOUTP/N
. Power Consumption (with 600Ω line load and 8Ω speaker load)
Max. Power
Consumption LIN-DRV SPK-DRV
Analog
Digital
Unit
Dis/Enable Dis/Enable
circuits
circuits
Operation
Stand-by
Disable
Disable
27
8 mA
Disable
Disable
27
8 mA
Operating
Enable
Disable
31
8
Disable
Enable
240
8
Enable
Enable
250
8
Power-down
Disable
Disable
460
335 uA
Power-down with SLEEP = 1 Disable
Disable
20
400 uA
@ Test condition : 1. at LIN-DRV (with 600Ω load) / SPK-DRV (with 8Ω load) full swing output
2. see LIN-DRV and SPK-DRV Descriptions
3. at the case of Temperature from -2¢ Jto 72¢ Jand Voltage from 4.4V to 5.6V
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX93002FC.PDF ] | |
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