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PDF MX7575JCWN Data sheet ( Hoja de datos )
| Número de pieza | MX7575JCWN | |
| Descripción | CMOS / uP-Compatible / 5s/10s / 8-Bit ADCs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-0876; Rev 1; 5/96
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________General Description
Maxim’s MX7575/MX7576 are high-speed (5µs/10µs),
microprocessor (µP) compatible, 8-bit analog-to-digital
converters (ADCs). The MX7575 provides an on-chip
track/hold function that allows full-scale signals up to
50kHz (386mV/µs slew rate) to be acquired and digi-
tized accurately. Both ADCs use a successive-approxi-
mation technique to achieve their fast conversions and
low power dissipation. The MX7575/MX7576 operate
with a +5V supply and a 1.23V external reference. They
accept input voltages ranging from 0V to 2VREF.
The MX7575/MX7576 are easily interfaced to all popu-
lar 8-bit µPs through standard CS and RD control sig-
nals. These signals control conversion start and data
access. A BUSY signal indicates the beginning and
end of a conversion. Since all the data outputs are
latched and three-state buffered, the MX7575/MX7576
can be directly tied to a µP data bus or system l/O port.
Maxim also makes the MAX165, a plug-in replacement
for the MX7575 with an internal 1.23V reference. For
applications that require a differential analog input and
an internal reference, the MAX166 is recommended.
________________________Applications
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
Audio Systems
High-Speed Servo Loops
Low-Power Data Loggers
_________________Pin Configurations
____________________________Features
o Fast Conversion Time: 5µs (MX7575)
10µs (MX7576)
o Built-In Track/Hold Function (MX7575)
o Low Total Unadjusted Error (±1LSB max)
o 50kHz Full-Power Signal Bandwidth (MX7575)
o Single +5V Supply Operation
o 8-Bit µP Interface
o 100ns Data-Access Time
o Low Power: 15mW
o Small-Footprint Packages
______________Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
INL
(LSB)
MX7575JN
0°C to +70°C 18 Plastic DIP ±1
MX7575KN
0°C to +70°C 18 Plastic DIP ±1/2
MX7575JCWN 0°C to +70°C 18 Wide SO
±1
MX7575KCWN 0°C to +70°C 18 Wide SO
±1/2
MX7575JP
0°C to +70°C 20 PLCC
±1
MX7575KP
0°C to +70°C 20 PLCC
±1/2
MX7575J/D
0°C to +70°C Dice*
±1
MX7575AQ
-25°C to +85°C 18 CERDIP**
±1
MX7575BQ
-25°C to +85°C 18 CERDIP**
±1/2
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
** Contact factory for availability.
_______________Functional Diagrams
TOP VIEW
CS 1
RD 2
TP (MODE) 3
BUSY 4
CLK 5
D7 (MSB) 6
D6 7
D5 8
DGND 9
MX7575
MX7576
18 VDD
17 REF
16 AIN
15 AGND
14 D0 (LSB)
13 D1
12 D2
11 D3
10 D4
( ) ARE FOR MX7576 ONLY.
DIP/SO
Pin Configurations continued at end of data sheet.
VDD
18
AIN 16 MX7575
AGND 15
REF 17
CLK 5
CLOCK
OSCILLATOR
TRACK/
HOLD
DAC
SAR
COMP
CS
RD
1
2
TP 3
CONTROL
LOGIC
LATCH AND
THREE-STATE
OUTPUT DRIVERS
4
BUSY
Functional Diagrams continued at end of data sheet.
9
DGND
..6
D7
D0
14
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
1 page  
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
D_
3k
100pF
+5V
3k
D_
100pF
D_
3k
+5V
3k
D_
10pF 10pF
DGND
DGND
a) HIGH-Z TO VOH
b) HIGH-Z TO VOL
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
Figure 1. Load Circuits for Data-Access Time Test
DGND
DGND
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
Figure 2. Load Circuits for Data-Hold Time Test
_______________Detailed Description
Converter Operation
The MX7575 and MX7576 use the successive-approxi-
mation technique to convert an unknown analog input
voltage to an 8-bit digital output code (see Functional
Diagrams). The MX7575 samples the input voltage on
an internal capacitor once (at the beginning of the con-
version), while the MX7576 samples the input signal
eight times during the conversion (see MX7575
Track/Hold and MX7576 Analog Input sections). The
internal DAC is initially set to half scale, and the com-
parator determines whether the input signal is larger
than or smaller than half scale. If it is larger than half
scale, the DAC MSB is kept. But if it is smaller, the MSB
is dropped. At the end of each comparison phase, the
SAR (successive-approximation register) stores the
results of the previous decision and determines the
next trial bit. This information is then loaded into the
DAC after each decision. As the conversion proceeds,
the analog input is approximated more closely by com-
paring it to the combination of the previous DAC bits
and a new DAC trial bit. After eight comparison cycles,
the eight bits stored in the SAR are latched into the out-
put latches. At the end of the conversion, the BUSY sig-
nal goes high, and the data in the output latches is
ready for microprocessor (µP) access. Furthermore, the
DAC is reset to half scale in preparation for the next
conversion.
Microprocessor Interface
The CS and RD logic inputs are used to initiate conver-
sions and to access data from the devices. The MX7575
and MX7576 have two common interface modes: slow-
memory interface mode and ROM interface mode. In
addition, the MX7576 has an asynchronous conversion
mode (MODE pin = low) where continuous conversions
are performed. In the slow-memory interface mode, CS
and RD are taken low to start a conversion and they
remain low until the conversion ends, at which time the
conversion result is latched. This mode is designed for
µPs that can be forced into a wait state. In the ROM
interface mode, however, the µP is not forced into a wait
state. A conversion is started by taking CS and RD low,
and data from the previous conversion is read. At the
end of the most recent conversion, the µP executes a
read instruction and starts another conversion.
For the MX7575, TP should be hard-wired to VDD to
ensure proper operation of the device. Spurious signals
may occur on TP, or excessive currents may be drawn
from VDD if TP is left open or tied to a voltage other than
VDD.
Slow-Memory Mode
Figure 3 shows the timing diagram for slow-memory
interface mode. This is used with µPs that have a wait-
state capability of at least 10µs (such as the 8085A),
where a read instruction is extended to accommodate
slow-memory devices. A conversion is started by exe-
cuting a memory read to the device (taking CS and RD
low). The BUSY signal (which is connected to the µP
READY input) then goes low and forces the µP into a
wait state. The MX7575 track/hold, which had been
tracking the analog input signal, holds the signal on the
third falling clock edge after RD goes low (Figure 12).
The MX7576, however, samples the analog input eight
times during a conversion (once before each compara-
tor decision). At the end of the conversion, BUSY
returns high, the output latches and buffers are updat-
ed with the new conversion result, and the µP com-
pletes the memory read by acquiring this new data.
The fast conversion time of the MX7575/MX7576
ensures that the µP is not forced into a wait state for an
excessive amount of time. Faster versions of many µPs,
_______________________________________________________________________________________ 5
5 Page 
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
+5V
R6
3.3k
0.1µF 47µF + ICL8069
1.2V
REFERENCE
+5V
47µF
+5V
TLC271
R5
5k
R4
8.2k
+5V
0.1µF
18
17
VDD
REF CLK
5
MX7575
RCLK
CL
100pF
2%
R1
1k
16 AIN
D7–D0
AGND
R8220Ω15
DGND
9
DATA OUT
R7 R3
10k 500Ω
INPUT VOLTAGE
Figure 18a. MX7575 Bipolar Configuration
__________Applications Information
Noise
To minimize noise coupling, keep both the input signal
lead to AIN and the signal return lead from AGND as
short as possible. If this is not possible, a shielded
cable or a twisted-pair transmission line is recommend-
ed. Additionally, potential differences between the ADC
ground and the signal-source ground should be mini-
mized, since these voltage differences appear as
errors superimposed on the input signal. To minimize
system noise pickup, keep the driving source resis-
tance below 2kΩ.
Proper Layout
For PC board layouts, take care to keep digital lines
well separated from any analog lines. Establish a sin-
gle-point, analog ground (separate from the digital sys-
tem ground) near the MX7575/MX7576. This analog
ground point should be connected to the digital system
ground through a single-track connection only. Any
supply or reference bypass capacitors, analog input fil-
ter capacitors, or input signal shielding should be
returned to the analog ground point.
OUTPUT
CODE
111...111
111...110
100...010
100...001 -FS
100...000 2
011...111
011...110
-1/2LSB
1/2LSB
AIN
FS -1LSB
2
000...001
000...000
FS = 2VREF
1LSB =
2FS
256
Figure 18b. Nominal Transfer Characteristic for Bipolar
Operation
__Functional Diagrams (continued)
AIN 16
AGND 15
MX7576
REF 17
CLK 5
CLOCK
OSCILLATOR
CS
RD
1
2
MODE 3
CONTROL
LOGIC
4
BUSY
VDD
18
COMP
DAC
SAR
LATCH AND
THREE-STATE
OUTPUT DRIVERS
9
DGND
..6
D7
D0
14
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MX7575JCWN.PDF ] | |
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