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87C196KS PDF даташит

Спецификация 87C196KS изготовлена ​​​​«Intel Corporation» и имеет функцию, называемую «ADVANCED 16-BIT CHMOS MICROCONTROLLER».

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Номер произв 87C196KS
Описание ADVANCED 16-BIT CHMOS MICROCONTROLLER
Производители Intel Corporation
логотип Intel Corporation логотип 

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87C196KS Даташит, Описание, Даташиты
87C196KT 87C196KS
ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
(b40 Cto a125 C Ambient)
Y High Performance CHMOS 16-Bit CPU
Y Up to 32 Kbytes of On-Chip EPROM
Y Up to 1 Kbyte of On-Chip Register RAM
Y Up to 512 Bytes of Additional RAM
(Code RAM)
Y Register-Register Architecture
Y 8 Channel 10-Bit A D with Sample Hold
Y 37 Prioritized Interrupt Sources
Y Up to Seven 8-Bit (56) I O Ports
Y Full Duplex Serial I O Port
Y Dedicated Baud Rate Generator
Y Interprocessor Communication Slave
Port
Y Selectable Bus Timing Modes for
Flexible Interfacing
Y Oscillator Fail Detection Circuitry
Y High Speed Peripheral Transaction
Server (PTS)
Y Two Dedicated 16-Bit High-Speed
Compare Registers
Y 10 High Speed Capture Compare (EPA)
Y Full Duplex Synchronous Serial I O
Port (SSIO)
Y Two Flexible 16-Bit Timer Counters
Y Quadrature Counting Inputs
Y Flexible 8- 16-Bit External Bus
(Programmable)
Y Programmable Bus (HLD HLDA)
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y 68-Pin PLCC Package
The 87C196Kx devices represents the 4th generation of MCS 96 microcontroller products implemented on
Intel’s advanced 1 micron process technology These products are based on the 80C196KB device with
enhancements ideal for automotive applications The instruction set is a true super set of the 80C196KB with a
few new instructions
The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU The
87C196KT is composed of the high speed (16 MHz) KX macrocore as well as the following peripherals Up to
32 Kbytes of Program EPROM up to 1 Kbytes of Register RAM (00-3FFH including SFRs) up to 512 bytes of
code RAM (16-bit addressing modes) with the ability to execute from this RAM space an eight channel-10 Bit
g3LSB analog to digital converter with programmable S H times with conversion times k20 ms at 16 MHz an
asynchronous synchronous serial I O port (8096 compatable) with a dedicated 16-bit baud rate generator an
additional synchronous serial I O port with full duplex master slave transceivers a flexible timer counter
structure with prescaler cascading and quadrature capabilities 10 modularized multiplexed high speed I O
for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs
and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS) The
PTS has several channel modes including single burst block transfers from any memory location to any
memory location a PWM and PWM toggle mode to be used in conjunction with the EPA and an A D scan
mode
Additional SFR space is allocated for the EPA and can be ‘‘windowed’’ into the lower Register RAM area
NOTICE
This datasheet contains information on products in production The specifications are subject to change
without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a
design
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1995
Order Number 270999-007
COPYRIGHT INTEL CORPORATION 1995
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87C196KS Даташит, Описание, Даташиты
87C196KT 87C196KS
Device Pins Package EPROM Reg RAM Code RAM I O EPA SIO SSIO A D
87C196KT 68-Pin PLCC
32K
1K
512b
56 10 Y
Y
8
87C196KS 68-Pin PLCC
24K
1K
256b
56 10 Y
Y
8
NOTE
This is a PRODUCT PREVIEW DATA SHEET The AC and DC parameters contained within this data sheet may change
after full automotive temperature characterization of the device has been performed Contact your local sales office before
finalizing the Timing and D C characteristics of a design to verify you have the latest information
ARCHITECTURE
The KT KS are new members of the MCS-96 family
having the same architecture and use the same in-
struction set as the 80C196KB Many new features
have been added including
CPU FEATURES
Y Powerdown and Idle Modes
Y 16 MHz Operating Frequency
Y A High Performance Peripheral
Transaction Server (PTS)
Y 37 Interrupt Vectors
Y Up to 512 Bytes of Additional Code
RAM
Y Up to 1 Kbyte of Additional Register
RAM
Y ‘‘Windowing’’ Allows 8-Bit Addressing
to some 16-Bit Addresses
Y 1 75 ms 16 x 16 Multiply
Y 3 ms 32 16 Divide
Y Oscillator Fail Detect Circuitry
PERIPHERAL FEATURES
Programmable A D Conversion and S H Times
10 Capture Compare I O with 2 Flexible Timers
(250 ns Resolution and Double Buffered Inputs)
Synchronous Serial I O Port for Full Duplex Seri-
al I O
Synchronous Asynchronous Serial I O Port
(with Dedicated 16-Bit Baud Rate Generator)
Total Utilization of ALL Available Pins (I O Mux’d
with Control)
(2) 16-Bit Timers with Prescale Cascading and
Quadrature Counting Capabilities
Up to 12 Externally Triggered Interrupts
NEW INSTRUCTIONS
XCH XCHB Exchange the contents of two loca-
tions either Word or Byte is support-
ed
BMOVI
Interruptable Block Move Instruction
allows the user to be interrupted dur-
ing long executing Block Moves
TIJMP
Table Indirect JUMP This instruction
incorportes a way to do complex
CASE level branches through one in-
struction An example of such code
savings several interrupt sources and
only one interrupt vector The TIJMP
instruction will sort through the sourc-
es and branch to the appropriate sub-
code level in one instruction This in-
struction was added especially for the
EPA structure but has other code sav-
ing advantages
EPTS DPTS Enable and Disable Interrupts (Works
like EI and DI)
SFR OPERATION
A total of 1 Kbyte of Register RAM is implemented
on the 87C196KT KS devices These locations sup-
port the on-chip peripherals that the 87C196KT KS
has (SFR’s) as well as offering a data storage area
These locations are all 8-bit directly addressable by
use of the windowing technique Any 32- 64- or 128-
byte section can be relocated into the upper 32- 64-
or 128-byte area of the Register RAM area 080H –
0FFH
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87C196KS Даташит, Описание, Даташиты
87C196KT Block Diagram
87C196KT 87C196KS
270999 – 1
270999 – 2
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Номер в каталогеОписаниеПроизводители
87C196KBCOMMERCIAL/EXPRESS CHMOS MICROCONTROLLERIntel Corporation
Intel Corporation
87C196KC16-BIT HIGH-PERFORMANCE CHMOS MICROCONTROLLERIntel Corporation
Intel Corporation
87C196KC16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLERIntel Corporation
Intel Corporation
87C196KCCommercial / Express CHMOS MicrocontrollerIntel
Intel

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