|
|
PDF 82443BX Data sheet ( Hoja de datos )
| Número de pieza | 82443BX | |
| Descripción | Host Bridge/Controller | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 82443BX (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Intel® 440BX AGPset:
82443BX Host Bridge/Controller
Datasheet
April 1998
Order Number: 290633-001
1 page  
Contents
1 Architectural Overview ...............................................................................................1-1
2 Signal Description ......................................................................................................2-1
2.1 Host Interface Signals...................................................................................2-1
2.2 DRAM Interface ............................................................................................2-3
2.3 PCI Interface (Primary) .................................................................................2-5
2.4 Primary PCI Sideband Interface ...................................................................2-6
2.5 AGP Interface Signals...................................................................................2-7
2.6 Clocks, Reset, and Miscellaneous ................................................................2-9
2.7 Power-Up/Reset Strap Options...................................................................2-10
3 Register Description...................................................................................................3-1
3.1 I/O Mapped Registers ...................................................................................3-2
3.1.1 CONFADD—Configuration Address Register..................................3-2
3.1.2 CONFDATA—Configuration Data Register .....................................3-3
3.1.3 PM2_CTL—ACPI Power Control 2 Control Register .......................3-4
3.2 PCI Configuration Space Access..................................................................3-4
3.2.1 Configuration Space Mechanism Overview .....................................3-5
3.2.2 Routing the Configuration Accesses to PCI or AGP ........................3-5
3.2.3 PCI Bus Configuration Mechanism Overview ..................................3-6
3.2.3.1 Type 0 Access ....................................................................3-6
3.2.3.2 Type 1 Access ....................................................................3-6
3.2.4 AGP Bus Configuration Mechanism Overview ................................3-6
3.2.5 Mapping of Configuration Cycles on AGP .......................................3-7
3.3 Host-to-PCI Bridge Registers (Device 0) ......................................................3-8
3.3.1 VID—Vendor Identification Register (Device 0).............................3-10
3.3.2 DID—Device Identification Register (Device 0) .............................3-10
3.3.3 PCICMD—PCI Command Register (Device 0) ..............................3-11
3.3.4 PCISTS—PCI Status Register (Device 0) .....................................3-12
3.3.5 RID—Revision Identification Register (Device 0) ..........................3-13
3.3.6 SUBC—Sub-Class Code Register (Device 0) ...............................3-13
3.3.7 BCC—Base Class Code Register (Device 0) ................................3-13
3.3.8 MLT—Master Latency Timer Register (Device 0)..........................3-14
3.3.9 HDR—Header Type Register (Device 0) .......................................3-14
3.3.10 APBASE—Aperture Base Configuration Register (Device 0)........3-14
3.3.11 SVID—Subsystem Vendor Identification Register (Device 0)........3-15
3.3.12 SID—Subsystem Identification Register (Device 0).......................3-16
3.3.13 CAPPTR—Capabilities Pointer Register (Device 0) ......................3-16
3.3.14 NBXCFG—NBX Configuration Register (Device 0) .......................3-16
3.3.15 DRAMC—DRAM Control Register (Device 0) ...............................3-19
3.3.16 DRAMT—DRAM Timing Register (Device 0) ................................3-20
3.3.17 PAM[6:0]—Programmable Attribute Map Registers(Device 0) ......3-20
3.3.18 DRB[0:7]—DRAM Row Boundary Registers (Device 0) ................3-22
3.3.19 FDHC—Fixed DRAM Hole Control Register (Device 0) ................3-24
3.3.20 MBSC—Memory Buffer Strength Control Register (Device 0) ......3-25
3.3.21 SMRAM—System Management RAM Control Register
(Device 0)‘......................................................................................3-28
82443BX Host Bridge Datasheet
v
5 Page 
Architectural Overview
1
The Intel® 440BX AGPset includes the 82443BX Host Bridge and the 82371EB PIIX4E for the
I/O subsystem. The 82443BX functions and capabilities include:
• Support for single and dual Pentium II processor configurations
• 64-bit GTL+ based Host Bus Interface
• 32-bit Host address Support
• 64-bit Main Memory Interface with optimized support for SDRAM at 100 and 66/60 MHz
• 32-bit Primary PCI Bus Interface (PCI) with integrated PCI arbiter
• AGP Interface (AGP) with 133 MHz data transfer capability configurable as a Secondary PCI
Bus
• Extensive Data Buffering between all interfaces for high throughput and concurrent operations
• Mobile and “Deep Green” Desktop power management support
Figure 1-1 shows a block diagram of a typical platform based on the Intel® 440BX AGPset. The
82443BX host bus interface supports up to two Pentium II processors at the maximum bus
frequency of 100 MHz. The physical interface design is based on the GTL+ specification optimized
for the desktop. The 82443BX provides an optimized 64-bit DRAM interface. This interface is
implemented as a 3.3V-only interface that supports only 3V DRAM technology. Two copies of the
MA, and CS# signals drive a maximum of two DIMMs each; providing unbuffered high
performance at 100 MHz. The 82443BX provides interface to PCI operating at
33 MHz. This interface implementation is compliant with PCI Rev 2.1 Specification. The
82443BX AGP interface implementation is based on Rev 1.0 of the AGP Specification. The AGP
interface supports 133 MHz data transfer rates and can be used as a Secondary PCI interface
operating at 66 MHz/3.3V supporting only a single PCI agent.
The 82443BX is designed to support the PIIX4E I/O bridge. PIIX4E is a highly integrated
multifunctional component supporting the following functions and capabilities:
• PCI Rev 2.1 compliant PCI-ISA Bridge with support for both 3.3V and 5V 33 MHz PCI
operations
• Deep Green Desktop Power Management Support
• Mobile Power Management Support
• Enhanced DMA controller and Interrupt Controller and Timer functions
• Integrated IDE controller with Ultra DMA/33 support
• USB host interface with support for 2 USB ports
• System Management Bus (SMB) with support for DIMM Serial PD
• Support for an external I/O APIC component
82443BX Host Bridge Datasheet
1-1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 82443BX.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 82443BX | Host Bridge/Controller | Intel Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |