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7LVC374APWDH PDF даташит

Спецификация 7LVC374APWDH изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State».

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Номер произв 7LVC374APWDH
Описание Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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7LVC374APWDH Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74LVC374A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger
(3-State)
Product specification
1998 Jul 29
Philips
Semiconductors









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7LVC374APWDH Даташит, Описание, Даташиты
Philips Semiconductors
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
Product specification
74LVC374A
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 2.7V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
High impedance when VCC = 0V
8-bit positive edge-triggered register
Independent register and 3-State buffer operation
DESCRIPTION
The 74LVC374A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC374A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs
that meet the setup and hold times requirements on the
LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The ’374’ is functionally identical to the ’574’, but the ’574’ has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; Tamb =25°C; tr = tf v 2.5ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
CP to Qn
CL = 50pF
VCC = 3.3V
fmax maximum clock frequency
CI Input capacitance
CPD
Power dissipation capacitance per
flip-flop
Notes 1 and 2
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL x VCC2 x fo) = sum of outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
20-Pin Plastic Shrink Small Outline (SO)
20-Pin Plastic Shrink Small Outline (SSOP) Type II
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
TEMPERATURE
OUTSIDE
RANGE
NORTH AMERICA
–40°C to +85°C 74LVC374A D
–40°C to +85°C 74LVC374A DB
–40°C to +85°C 74LVC374A PW
TYPICAL
4.8
150
5.0
20
NORTH AMERICA
74LVC374A D
74LVC374A DB
7LVC374APW DH
UNIT
ns
MHz
pF
pF
PKG. DWG. #
SOT163-1
SOT339-1
SOT360-1
1998 Jul 29
2 853-1861 19802









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7LVC374APWDH Даташит, Описание, Даташиты
Philips Semiconductors
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
Product specification
74LVC374A
PIN CONFIGURATION
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
SA00389
PIN DESCRIPTION
PIN NUMBER SYMBOL
FUNCTION
1
3, 4, 7, 8, 13,
14, 17, 18
OE
D0-D7
Output enable input (active-Low)
Data inputs
2, 5, 6, 9, 12,
15, 16, 19
11
10
Q0-Q7
CP
GND
3-state flip-flop outputs
Clock input (LOW-to-HIGH,
edge-triggered)
Ground (0V)
20 VCC Positive supply voltage
LOGIC SYMBOL
11
3
D0 CP
Q0
4 D1
Q1
7 D2
Q2
8 D3
13 D4
Q3
Q4
14 D5
Q5
17 D6
Q6
18 D7 OE Q7
2
5
6
9
12
15
16
19
1
SA00390
LOGIC SYMBOL (IEEE/IEC)
11
C1
1 EN1
3 1D
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
SA00391
FUNCTIONAL DIAGRAM
3 D0
4 D1
7 D2
8 D3
13 D4
14 D5
17 D6
18 D7
11 CP
1 OE
FF1
to
FF8
Q0
Q1
Q2
3-State
OUTPUTS
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
SA00392
1998 Jul 29
3










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NXP Semiconductors

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