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74LVCH32373A PDF даташит

Спецификация 74LVCH32373A изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state».

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Номер произв 74LVCH32373A
Описание 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVCH32373A Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
74LVCH32373A
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
Product specification
File under Integrated Circuits, IC24
1999 Nov 24









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74LVCH32373A Даташит, Описание, Даташиты
Philips Semiconductors
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
Product specification
74LVCH32373A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTEflow-trough standard pin-out architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
Bus hold on data inputs
Typical output ground bounce voltage:
VOLP < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
Typical output undershoot voltage:
VOHV > 2 V at VCC = 3.3 V and Tamb = 25 °C
Power off disables outputs, permitting live insertion
Packaged in plastic fine-pitch ball grid array package.
DESCRIPTION
The 74LVCH32373A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices in a mixed
3.3 or 5 V environment.
The 74LVCH32373A is a 32-bit transparent D-type latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One latch enable
(nLE) input and one output enable (nOE) are provided for
each octal. Inputs can be driven from either 3.3 or 5 V
devices.
The 74LVCH32373A consists of 4 sections of eight D-type
transparent latches with 3-state true outputs. When input
nLE is HIGH, data at the nDn inputs enter the latches. In
this condition the latches are transparent, i.e. a latch
output will change each time its corresponding D-input
changes.
When input nLE is LOW the latches store the information
that was present at the D-inputs one set-up time preceding
the HIGH-to-LOW transition of nLE. When input nOE is
LOW, the contents of the eight latches are available at the
outputs. When input nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.
The 74LVCH32373A bus hold data input circuits eliminate
the need for external pull-up resistors to hold unused
inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH
CI
CPD
propagation delay
nDn to nQn
nLE to nQn
input capacitance
power dissipation capacitance
per buffer
CONDITIONS
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
VI = GND to VCC; note 1
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ (CL × VCC2 × fo) = sum of the outputs.
TYPICAL
UNIT
3.0 ns
3.4 ns
5.0 pF
26 pF
1999 Nov 24
2









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74LVCH32373A Даташит, Описание, Даташиты
Philips Semiconductors
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
Product specification
74LVCH32373A
FUNCTION TABLE
See note 1.
OPERATING MODE
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable
outputs
nOE
L
L
L
L
H
H
INPUTS
nLE
H
H
L
L
L
L
INTERNAL
nDn LATCHES
LL
HH
lL
hH
lL
hH
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
OUTPUTS
nQn
L
H
L
H
Z
Z
ORDERING INFORMATION
TYPE NUMBER
74LVCH32373AEC
TEMPERATURE RANGE
40 to +85 °C
PACKAGE
PINS PACKAGE MATERIAL CODE
96 LFBGA96 plastic SOT536-1
PINNING
SYMBOL
nDn
nLE
nQn
GND
nOE
VCC
data inputs
latch enable inputs (active HIGH)
data outputs
ground (0 V)
output enable inputs (active LOW)
DC supply voltage
DESCRIPTION
1999 Nov 24
3










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Номер в каталогеОписаниеПроизводители
74LVCH32373A32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-stateNXP Semiconductors
NXP Semiconductors
74LVCH32373AEC32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-stateNXP Semiconductors
NXP Semiconductors

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