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PHD96NQ03LT PDF даташит

Спецификация PHD96NQ03LT изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «N-channel enhancement mode field-effect transistor».

Детали детали

Номер произв PHD96NQ03LT
Описание N-channel enhancement mode field-effect transistor
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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PHD96NQ03LT Даташит, Описание, Даташиты
PHP/PHB/PHD96NQ03LT
N-channel enhancement mode field-effect transistor
Rev. 03 — 23 October 2001
Product data
1. Description
N-channel logic level field-effect power transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
PHP96NQ03LT in SOT78 (TO-220AB)
PHB96NQ03LT in SOT404 (D2-PAK)
PHD96NQ03LT in SOT428 (D-PAK).
2. Features
s Low gate charge
s Low on-state resistance.
3. Applications
s Optimized as a control FET in DC to DC converters.
4. Pinning information
Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
mb
[1]
mb
mb
3 source (s)
mb mounting base,
connected to drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
2
1
Top view
3
MBK091
SOT428 (D-PAK)
Symbol
g
MBB076
d
s
[1] It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.
1. TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.









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PHD96NQ03LT Даташит, Описание, Даташиты
Philips Semiconductors
PHP/PHB/PHD96NQ03LT
N-channel enhancement mode field-effect transistor
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter
VDS
ID
Ptot
Tj
RDSon
drain-source voltage (DC)
drain current (DC)
total power dissipation
junction temperature
drain-source on-state resistance
6. Limiting values
Conditions
Tj = 25 to 175 °C
Tmb = 25 °C; VGS = 5 V
Tmb = 25 °C
Tj = 25° C; VGS = 10 V; ID = 25 A
Tj = 25° C; VGS = 5 V; ID = 25 A
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
VDGR
VGS
VGSM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
gate-source voltage
ID drain current (DC)
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj operating junction temperature
Source-drain diode
Tj = 25 to 175 °C
Tj = 25 to 175 °C; RGS = 20 k
tp 50 µs; pulsed;
duty cycle 25%; Tj 150 °C
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
Tmb = 100 °C; VGS = 5 V; Figure 2
Tmb = 25 °C; pulsed; tp 10 µs; Figure 3
Tmb = 25 °C; Figure 1
IS source (diode forward) current (DC) Tmb = 25 °C
ISM peak source (diode forward) current Tmb = 25 °C; pulsed; tp 10 µs
Typ Max Unit
- 25 V
- 75 A
- 115 W
- 175 °C
4.2 4.95 m
5.6 7.5 m
Min Max Unit
- 25 V
- 25 V
- ±15 V
- ±20 V
- 75 A
- 65 A
- 240 A
- 115 W
55 +175 °C
55 +175 °C
- 75 A
- 240 A
9397 750 08963
Product data
Rev. 03 — 23 October 2001
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
2 of 14









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PHD96NQ03LT Даташит, Описание, Даташиты
Philips Semiconductors
PHP/PHB/PHD96NQ03LT
N-channel enhancement mode field-effect transistor
120
Pder
(%)
80
03aa16
120
Ider
(%)
80
03af09
40 40
0
0 50 100 150 200
Tmb (oC)
Pder = P-------P----t--o--t------- × 100%
t o t ( 25 °C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
0
0 50 100 150 200
Tmb (ºC)
Ider = -I------I---D-------- × 100%
D ( 25 °C )
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
103
ID
(A) RDSon = VDS / ID
102
10
DC
tp = 10 µs
100 µs
1 ms
10 ms
100 ms
03af11
1
1 10 102
VDS (V)
Tmb = 25 °C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 08963
Product data
Rev. 03 — 23 October 2001
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
3 of 14










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