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74LCX32373GX PDF даташит

Спецификация 74LCX32373GX изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 32-Bit Transparent Latch with 5V Tolerant Inputs and Outputs Preliminary».

Детали детали

Номер произв 74LCX32373GX
Описание Low Voltage 32-Bit Transparent Latch with 5V Tolerant Inputs and Outputs Preliminary
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LCX32373GX Даташит, Описание, Даташиты
Preliminary
January 2001
Revised August 2001
74LCX32373
Low Voltage 32-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs (Preliminary)
General Description
The LCX32373 contains thirty-two non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCX32373 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCX32373 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
I 5V tolerant inputs and outputs
I 2.3V–3.6V VCC specifications provided
I 5.4 ns tPD max (VCC = 3.3V), 20 µA ICC max
I Power down high impedance inputs and outputs
I Supports live insertion/withdrawal (Note 1)
I ±24 mA output drive (VCC = 3.0V)
I Uses patented noise/EMI reduction circuitry
I Latch-up performance exceeds 500 mA
I ESD performance:
Human body model > 2000V
Machine model > 200V
I Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
(Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX32373GX
(Note 2)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
Note 2: BGA package available in Tape and Reel only.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500547
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74LCX32373GX Даташит, Описание, Даташиты
Preliminary
Connection Diagram
(Top Thru View)
Pin Descriptions
Pin Names
OEn
LEn
I0 - I31
O0 - O31
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
FBGA Pin Assignments
12
A O1 O0
B O3 O2
C O5 O4
D O7 O6
E O9 O8
F O11 O10
G O13 O12
H
O14
O15
J O17 O16
K
O19
O18
L O21 O20
M O23 O22
N
O25
O24
P O27 O26
R O29 O28
T O30 O31
Truth Table
3
OE1
GND
VCC
GND
GND
VCC
GND
OE2
OE3
GND
VCC
GND
GND
VCC
GND
OE4
4
LE1
GND
VCC
GND
GND
VCC
GND
LE2
LE3
GND
VCC
GND
GND
VCC
GND
LE4
5
I0
I2
I4
I6
I8
I10
I12
I15
I16
I18
I20
I22
I24
I26
I28
I31
6
I1
I3
I5
I7
I9
I11
I13
I14
I17
I19
I21
I23
I25
I27
I29
I30
Functional Description
The LCX32373 contains thirty-two D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
32-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the In enters the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time
Inputs
Outputs
LEn OEn
In
On
XH
X
Z
HL
L
L
HL
H
H
LL
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The
3-STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard out-
puts are in the 2-state mode. When OEn is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
www.fairchildsemi.com
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74LCX32373GX Даташит, Описание, Даташиты
Logic Diagrams
Preliminary
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Fairchild Semiconductor

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