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Número de pieza | 74HCT191 | |
Descripción | Presettable synchronous 4-bit binary up/down counter | |
Fabricantes | Philips | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 74HCT191 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT191
Presettable synchronous 4-bit
binary up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990
1 page Philips Semiconductors
Presettable synchronous 4-bit binary
up/down counter
Product specification
74HC/HCT191
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
parallel load
count up
count down
hold (do nothing)
INPUTS
PL U/D CE CP
LXXX
LXXX
HL I ↑
HH I ↑
HXHX
Dn
L
H
X
X
X
TC AND RC FUNCTION TABLE
INPUTS
TERMINAL COUNT STATE
U/D CE CP Q0
Q1
Q2 Q3
HHXH H
LHXH H
LL
HH
LHXL
L
HHX L
L
HL
LL
HH
HH
HH
LL
LL
LL
Notes
1. H = HIGH voltage level
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition
= one LOW level pulse
= TC goes LOW on a LOW-to-HIGH CP transition
OUTPUTS
Qn
L
H
count up
count down
no change
OUTPUTS
TC RC
LH
HH
LH
HH
December 1990
5
5 Page Philips Semiconductors
Presettable synchronous 4-bit binary
up/down counter
Product specification
74HC/HCT191
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
+25
min. typ. max.
74HC
−40 to +85
min. max.
−40 to +125
min. max.
UNIT
VCC
(V)
WAVEFORMS
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tPHL/ tPLH
tTHL/ tTLH
propagation delay
CP to Qn
propagation delay
CP to TC
propagation delay
CP to RC
propagation delay
CE to RC
propagation delay
Dn to Qn
propagation delay
PL to Qn
propagation delay
U/D to TC
propagation delay
U/D to RC
output transition time
26 48
32 51
19 35
19 33
22 44
27 46
23 45
24 45
7 15
60 72 ns 4.5 Fig.10
64 77 ns 4.5 Fig.10
44 53 ns 4.5 Fig.11
41 50 ns 4.5 Fig.11
55 66 ns 4.5 Fig.12
58 69 ns 4.5 Fig.13
56 68 ns 4.5 Fig.14
56 68 ns 4.5 Fig.14
19 22 ns 4.5 Fig.15
tW clock pulse width 16 9 20 24 ns 4.5 Fig.10
HIGH or LOW
tW parallel load pulse width 22 11
28
33
ns 4.5 Fig.15
LOW
trem removal time
PL to CP
71
9
11 ns 4.5 Fig.15
tsu set-up time
U/D to CP
41 20
51
62 ns 4.5 Fig.17
tsu set-up time
Dn to PL
tsu set-up time
CE to CP
20 9
30 18
25
38
30 ns 4.5 Fig.16
45 ns 4.5 Fig.17
th hold time
U/D to CP
0 −18
0
0 ns 4.5 Fig.17
th hold time
Dn to PL
th hold time
CE to CP
0 −5
0 −10
0
0
0 ns 4.5 Fig.16
0 ns 4.5 Fig.17
fmax maximum clock pulse 20 33
16
13
MHz 4.5 Fig.10
frequency
December 1990
11
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet 74HCT191.PDF ] |
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