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PDF TLIU04C1 Data sheet ( Hoja de datos )
| Número de pieza | TLIU04C1 | |
| Descripción | TLIU04C1 Quad T1/E1 Line Interface | |
| Fabricantes | Agere Systems | |
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Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
Features
s Selectable microprocessor or direct logic control
modes.
s Quad T1/E1 line interface.
s Hardware and software reset options.
s 3-state outputs.
s 0.35 µm CMOS technology.
s Compliant with:
AT&T
CB119 (10/79)
Bellcore
TR-54016 (89)
TR-TSY-000170 (10/97)
TR-TSY-000009 (5/86)
GR-499-CORE (12/95)
GR-253-CORE (12/95)
ANSI
T1.102 (93)
T1.231 (93)
T1.403 (95)
ITU-T
G.703 (88)
G.704 (91)
G.706 (91)
G.732 (88)
G.735-9 (88)
G.775 (11/94)
G.823-4 (3/93)
G.826 (11/93)
I.431 (3/93)
ETSI
TBR 12 (12/93)
TBR 13 (1/96)
s –40 °C to +85 °C operating temperature range.
s Fine-pitch (12.5 mil) surface-mount
package, 144-pin TQFP.
s Transmitter includes transmit encoder (B8ZS or
HDB3), pulse shaping, and line driver.
s Five pulse equalization settings for template com-
pliance at DSX cross connect.
s Receive includes equalization, digital clock and
data recovery (immune to false lock), and receive
decoder (B8ZS or HDB3).
s CEPT/E1 interference immunity as required by
G.703.
s Transmit jitter <0.02 UI.
s Receive generated jitter <0.05 UI.
s Jitter attenuator selectable for use in transmit or
receive path. Jitter attenuation characteristics are
data pattern independent.
s For use with 100 Ω DS1 twisted-pair, 120 Ω E1
twisted-pair, and 75 Ω E1 coaxial cable.
s Common part available for transmit/receive
transformers.
s Analog LOS alarm for signals less than –18 dB for
greater than 1 ms or 10 bit symbol periods to
255 bit symbol periods (selectable).
s Digital LOS alarm for 100 zeros (DS1) or 255 zeros
(CEPT).
s Diagnostic loopback modes.
s Low power consumption.
Applications
s T1/E1 network performance monitoring
s SONET/SDH multiplexers
s Asynchronous multiplexers (M13)
s Digital access cross connects (DACs)
s Channel banks
s Digital radio base stations, remote wireless mod-
ules
s PBX interface
1 page  
Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
Figures
List of Figures
Page
Figure 1. TLIU04C1 Microprocessor Mode Pin Diagram.......................................................................................... 9
Figure 2. TLIU04C1 Block Diagram, CMODE = 1 (Microprocessor Mode) ............................................................ 18
Figure 3. Block Diagram of the Quad Line Interface Unit (Single Channel) ........................................................... 19
Figure 4. DS1/T1 Receiver Jitter Accommodation Without Jitter Attenuator .......................................................... 24
Figure 5. DS1/T1 Receiver Jitter Transfer Without Jitter Attenuator ...................................................................... 25
Figure 6. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator ....................................................... 27
Figure 7. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator ................................................................... 28
Figure 8. DSX-1 Isolated Pulse Template .............................................................................................................. 31
Figure 9. ITU-T G.703 Pulse Template .................................................................................................................. 33
Figure 10. DS1/T1 Receiver Jitter Accommodation with Jitter Attenuator.............................................................. 37
Figure 11. DS1/T1 Jitter Transfer of the Jitter Attenuator....................................................................................... 38
Figure 12. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator ........................................................... 39
Figure 13. CEPT/E1 Jitter Transfer of the Jitter Attenuator.................................................................................... 40
Figure 14. Line Termination Circuitry ..................................................................................................................... 50
Figure 15. Mode 1—Read Cycle Timing (MPMODE = 0, MPMUX = 0) ................................................................. 55
Figure 16. Mode 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0) ................................................................. 55
Figure 17. Mode 2—Read Cycle Timing (MPMODE = 0, MPMUX = 1) ................................................................. 56
Figure 18. Mode 2—Write Cycle Timing (MPMODE = 0, MPMUX = 1) ................................................................. 56
Figure 19. Mode 3—Read Cycle Timing (MPMODE = 1, MPMUX = 0) ................................................................. 57
Figure 20. Mode 3—Write Cycle Timing (MPMODE = 1, MPMUX = 0) ................................................................. 57
Figure 21. Mode 4—Read Cycle Timing (MPMODE = 1, MPMUX = 1) ................................................................. 58
Figure 22. Mode 4—Write Cycle Timing (MPMODE = 1, MPMUX = 1) ................................................................. 58
Figure 23. Interface Data Timing (ACM = 0)........................................................................................................... 59
Figure 24. TLIU04C1 Direct Logic Control Mode Pin Diagram............................................................................... 61
Figure 25. TLIU04C1 Block Diagram, CMODE = 0 (Direct Logic Mode)................................................................ 67
Figure 26. Block Diagram of the Quad Line Interface Unit (Single Channel) ......................................................... 68
Figure 27. DS1/T1 Receiver Jitter Accommodation Without Jitter Attenuator ........................................................ 73
Figure 28. DS1/T1 Receiver Jitter Transfer Without Jitter Attenuator .................................................................... 74
Figure 29. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator ..................................................... 76
Figure 30. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator ................................................................. 77
Figure 31. DSX-1 Isolated Pulse Template ............................................................................................................ 80
Figure 32. ITU-T G.703 Pulse Template ................................................................................................................ 81
Figure 33. DS1/T1 Receiver Jitter Accommodation with Jitter Attenuator.............................................................. 85
Figure 34. DS1/T1 Jitter Transfer of the Jitter Attenuator....................................................................................... 86
Figure 35. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator ........................................................... 87
Figure 36. CEPT/E1 Jitter Transfer of the Jitter Attenuator.................................................................................... 88
Figure 37. Line Termination Circuitry ..................................................................................................................... 94
Figure 38. Interface Data Timing (ACM = 0)........................................................................................................... 97
Lucent Technologies Inc.
5
5 Page 
Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
Microprocessor Mode (continued)
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Pin Symbol Type*
Name/Description
138, 19, RPD/RDATA
66, 91
[1—4]
139, 18, RCLK/ALOS
67, 90
[1—4]
140, 17, TND[1—4]
68, 89
O Receive Positive Data. When in dual-rail (DUAL = 1: register 5, bit 4) clock
recovery mode (CDR = 1: register 5, bit 0), this signal is the received positive
NRZ data to the terminal equipment. When in data slicing mode (CDR = 0),
this signal is the raw sliced positive data of the front end.
Receive Data. When in single-rail (DUAL = 0: register 5, bit 4) clock recovery
mode (CDR = 1: register 5, bit 0), this signal is the received NRZ data.
O Receive Clock. In clock recovery mode (CDR = 1: register 5, bit 0), this
signal is the recovered receive clock for the terminal equipment. The duty
cycle of RCLK is 50% ± 5%.
Analog Loss of Signal. In data slicing mode (CDR = 0: register 5, bit 0), this
signal is asserted high to indicate low amplitude receive data at the RTIP/
RRING inputs.
I Transmit Negative Data. This signal is the transmit negative NRZ data from
the terminal equipment.
141, 16, TPD/TDATA
69, 88
[1—4]
142, 15,
70, 87
110
TCLK[1—4]
MPMODE
108 MPMUX
107 WR_DS
I Transmit Positive Data. When in dual-rail mode (DUAL = 1: register 5, bit 4),
this signal is the transmit positive NRZ data from the terminal equipment.
Transmit Data. When in single-rail mode (DUAL = 0: register 5, bit 4), this
signal is the transmit NRZ data from the terminal equipment.
I Transmit Clock. DS1 (1.544 MHz ± 32 ppm) or CEPT (2.048 MHz ±
50 ppm) clock signal from the terminal equipment.
I Microprocessor Mode. When MPMODE = 1, the device uses the address
latch enable type microprocessor read/write protocol with separate read and
write controls. Setting MPMODE = 0 allows the device to use the address
strobe type microprocessor read/write protocol with a separate data strobe
and a combined read/write control.
I Microprocessor Multiplex Mode. Setting MPMUX = 1 allows the
microprocessor interface to accept multiplexed address and data signals.
Setting MPMUX = 0 allows the microprocessor interface to accept
demultiplexed (separate) address and data signals.
I Write (Active-Low). If MPMODE = 1 (pin 110), this pin is asserted low by the
microprocessor to initiate a write cycle.
Data Strobe (Active-Low). If MPMODE = 0 (pin 21), this pin becomes the
data strobe for the microprocessor. When R/W = 0 (pin 111) initiating a write,
a low applied to this pin latches the signal on the data bus into internal
registers.
111 RD_R/W
I Read (Active-Low). If MPMODE = 1 (pin 110), this pin is asserted low by the
microprocessor to initiate a read cycle.
Read/Write. If MPMODE = 0 (pin 110), this pin is asserted high by the
microprocessor to initiate a read cycle or asserted low to initiate a write
cycle.
* I = input, O = output, Iu indicates an input with internal pull-up; Id indicates an input with internal pull-down, P = power. Resistance value of all
internal pull-ups or pull-downs is 50 kΩ, unless otherwise specified.
Lucent Technologies Inc.
11
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