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PDF TP3404V Data sheet ( Hoja de datos )
| Número de pieza | TP3404V | |
| Descripción | Quad Digital Adapter for Subscriber Loops (QDASL) | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TP3404V (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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PRELIMINARY
July 1994
TP3404
Quad Digital Adapter for Subscriber Loops (QDASL)
General Description
The TP3404 is a combination 4-line transceiver for voice
and data transmission on twisted pair subscriber loops typi-
cally in PBX line card applications It is a companion device
to the TP3401 2 3 DASL single-channel transceivers In
addition to 4 independent transceivers a time-slot assign-
ment circuit is included to support interfacing to the system
backplane
Each QDASL line operates as an ISDN ‘‘U’’ Interface for
short loop applications typically in a PBX environment pro-
viding transmission for 2 B channels and 1 D channel
Full-duplex transmission at 144 kb s is achieved on single
twisted wire pairs using a burst-mode technique (Time Com-
pression Multiplexed) All timing sequences necessary for
loop activation and de-activation are generated on-chip
Alternate Mark Inversion (AMI) line coding is used to ensure
low error rates in the presence of noise with lower emi radia-
tion than other codes such as Biphase (Manchester) On
24 AWG cable the range is at least 1 8 km (6k ft)
Features
4 COMPLETE ISDN PBX 2-WIRE DATA TRANSCEIVERS
INCLUDING
Y Quad 2 B plus D channel interface for PBX ‘‘U’’
interface
Y 144 kb s full-duplex on 1 twisted pair using Burst Mode
Transmission Technique
Y Loop range up to 6 kft ( 24AWG)
Y Alternate Mark Inversion coding with transmit Pulse
Shaping DAC Smoothing Filter and scrambler for low
emi radiation
Y Adaptive line equalizer
Y On-chip timing recovery no external components
Y Programmable Time-Slot Assignment TDM interface for
B channels
Y Separate interface for D channel with Programmable
Sub-Slot Assignment
Y 4 096 MHz master clock
Y 4 loop-back test modes
Y MICROWIRETM compatible serial control interface
Y 5V operation
Y 28-pin PLCC package
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation
MICROWIRETM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 11924
TL H 11924 – 1
RRD-B30M115 Printed in U S A
1 page  
Connection Diagram
Top View
TL H 11924 – 2
Order Number TP3404V
See NS Package Number V28A
Functional Description
The QDASL contains 4 transceivers each of which can in-
teroperate with any of the TP340X family of single-channel
DASL transceivers Each QDASL transceiver has its own
independent line transmit and receive section timing recov-
ery circuit scrambler descrambler and loop activation con-
troller Functions which are shared by the 4 transceivers
include the Microwire control port and the digital interface
with time-slot assignment
BURST MODE OPERATION
For full-duplex operation over a single twisted-pair burst
mode timing is used with the QDASL end of each line act-
ing as the loop timing master and the DASL at the terminal
being the timing slave (the QDASL transceivers cannot op-
erate in loop timing slave mode)
Each burst within a DASL line is initiated by the QDASL
Master transmitting a startbit for burst framing followed by
the B1 B2 and D channel data from 2 consecutive 8 kHz
frames combined in the format shown in Figure 1 During
transmit bursts the receiver input for that channel is inhibit-
ed to avoid disturbing the adaptive circuits The slave’s re-
ceiver is enabled at this time and it synchronizes to the start
bit of the burst which is always an unscrambled ‘‘1’’ (of the
opposite polarity to the last ‘‘1’’ sent in the previous burst)
When the slave detects that 36 bits following the start bit
have been received it disables the received input waits 6
line symbol periods to match the other end settling guard
time and then begins to transmit its burst back towards the
master which by this time has enabled its receiver input
The burst repetition rate is thus 4 KHz
LINE TRANSMIT SECTIONS
Alternate Mark Inversion (AMI) line coding in which binary
‘‘1’’s are alternately transmitted as a positive pulse then a
negative pulse is used on each DASL line because of its
spectral efficiency and null DC energy content All transmit-
ted bits excluding the start bit are scrambled by a 9-bit
scrambler to provide good spectral spreading with a strong
timing content The scrambler feedback polynomial is X9 a
X5 a 1
FIGURE 1 Burst Mode Timing on the Line
5
TL H 11924 – 3
5 Page 
Applications Information (Continued)
FIGURE 5 Typical Application
11
TL H 11924 – 7
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet TP3404V.PDF ] | |
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