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PDF TP3064N Data sheet ( Hoja de datos )
| Número de pieza | TP3064N | |
| Descripción | Enhanced Serial Interface CMOS CODEC/Filter COMBO | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 1991
TP3064 TP3067
‘‘Enhanced’’ Serial Interface
CMOS CODEC Filter COMBO
General Description
The TP3064 (m-law) and TP3067 (A-law) are monolithic
PCM CODEC Filters utilizing the A D and D A conversion
architecture shown in Figure 1 and a serial PCM interface
The devices are fabricated using National’s advanced dou-
ble-poly CMOS process (microCMOS)
Similar to the TP305X family these devices feature an addi-
tional Receive Power Amplifier to provide push-pull bal-
anced output drive capability The receive gain can be ad-
justed by means of two external resistors for an output level
of up to g6 6V across a balanced 600X load
Also included is an Analog Loopback switch and a TSX out-
put
See also AN-370 ‘‘Techniques for Designing with CODEC
Filter COMBO Circuits ’’
COMBO and TRI-STATE are registered trademarks of National Semiconductor Corpora-
tion
Features
Y Complete CODEC and filtering system including
Transmit high-pass and low-pass filtering
Receive low-pass filter with sin x x correction
Active RC noise filters
m-law or A-law compatible COder and DECoder
Internal precision voltage reference
Serial I O interface
Internal auto-zero circuitry
Receive push-pull power amplifiers
Y m-law TP3064
Y A-law TP3067
Y Designed for D3 D4 and CCITT applications
Y g5V operation
Y Low operating power typically 70 mW
Y Power-down standby mode typically 3 mW
Y Automatic power-down
Y TTL or CMOS compatible digital interfaces
Y Maximizes line interface card circuit density
Block Diagram
C1995 National Semiconductor Corporation TL H 5070
FIGURE 1
TL H 5070 – 1
RRD-B30M115 Printed in U S A
1 page  
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
VCC to GNDA
VBB to GNDA
Voltage at any Analog Input
or Output
7V
b7V
VCCa0 3V to VBBb0 3V
Voltage at any Digital Input
or Output
VCCa0 3V to GNDAb0 3V
Operating Temperature Range
b25 C to a125 C
Storage Temperature Range
b65 C to a150 C
Lead Temp (Soldering 10 sec )
300 C
ESD (Human Body Model) J
1000V
ESD (Human Body Model) N
1500V
Latch-Up Immunity
100 mA on Any Pin
Electrical Characteristics Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e
a5 0V g5% VBB e b5 0V g5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits
are assured by correlation with other production tests and or product design and characterization All signals referenced to
GNDA Typicals specified at VCC e a5 0V VBB e b5 0V TA e 25 C
Symbol
Parameter
Conditions
Min Typ Max Units
POWER DISSIPATION (ALL DEVICES)
ICC0
Power-Down Current
IBB0
Power-Down Current
ICC1
Active Current
IBB1
Active Current
DIGITAL INTERFACE
(Note)
(Note)
VPIe0V VFRO VPOa and VPOb unloaded
VPIe0V VFRO VPOa and VPOb unloaded
05 15
0 05 0 3
7 0 10 0
7 0 10 0
mA
mA
mA
mA
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
DX ILe3 2 mA
TSX ILe3 2 mA Open Drain
VOH
Output High Voltage
DX IHeb3 2 mA
IIL Input Low Current
GNDAsVINsVIL All Digital Inputs
IIH Input High Current
VIHsVINsVCC
IOZ Output Current in High Impedance DX GNDAsVOsVCC
State (TRI-STATE)
Note ICC0 and IBB0 are measured after first achieving a power-up state
22
24
b10
b10
b10
06 V
V
04 V
04 V
V
10 mA
10 mA
10 mA
5
5 Page 
Transmission Characteristics (Continued)
Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e a5 0V g5% VBB e b5 0V g5% TA e
0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other
production tests and or product design and characterization GNDA e 0V f e 1 02 kHz VIN e 0 dbm0 transmit input amplifier
connected for unity gain non-inverting Typicals specified at VCC e a5 0V VBB e b5 0V TA e 25 C
Symbol
Parameter
Conditions
Min Typ Max
Units
ENVELOPE DELAY DISTORTION WITH FREQUENCY
DXA Transmit Delay Absolute
fe1600 Hz
DXR
Transmit Delay Relative to DXA
fe500 Hzb600 Hz
fe600 Hzb800 Hz
fe800 Hzb1000 Hz
fe1000 Hzb1600 Hz
fe1600 Hzb2600 Hz
fe2600 Hzb2800 Hz
fe2800 Hzb3000 Hz
290 315
195 220
120 145
50 75
20 40
55 75
80 105
130 155
ms
ms
ms
ms
ms
ms
ms
ms
DRA Receive Delay Absolute
fe1600 Hz
DRR
Receive Delay Relative to DRA
fe500 Hzb1000 Hz
fe1000 Hzb1600 Hz
fe1600 Hzb2600 Hz
fe2600 Hzb2800 Hz
fe2800 Hzb3000 Hz
b40
b30
180
b25
b20
70
100
145
200
90
125
175
ms
ms
ms
ms
ms
ms
NOISE
NXC Transmit Noise C Message
Weighted
TP3064 (Note 1)
12 15 dBrnC0
NXP Transmit Noise Psophometric TP3067 (Note 1)
Weighted
b74 b67 dBm0p
NRC Receive Noise C Message
Weighted
PCM Code Equals Alternating
Positive and Negative Zero
TP3064
8 11 dBrnCO
NRP Receive Noise Psophometric
Weighted
PCM Code Equals Positive
Zero
TP3067
b82 b79 dBm0p
NRS
PPSRX
Noise Single Frequency
Positive Power Supply Rejection
Transmit
fe0 kHz to 100 kHz Loop Around
Measurement VFXIa e0 Vrms
VCCe5 0 VDCa100 mVrms
fe0 kHzb50 kHz (Note 2)
40
b53
dBm0
dBC
NPSRX
Negative Power Supply Rejection
Transmit
VBBeb5 0 VDCa 100 mVrms
fe0 kHzb50 kHz (Note 2)
40
dBC
PPSRR
Positive Power Supply Rejection
Receive
PCM Code Equals Positive Zero
VCCe5 0 VDCa100 mVrms
Measure VFRO
fe0 Hzb4000 Hz
fe4 kHzb50 kHz
38
25
dBC
dB
NPSRR
Negative Power Supply Rejection
Receive
PCM Code Equals Positive Zero
VBBeb5 0 VDCa100 mVrms
Measure VFRO
fe0 Hzb4000 Hz
fe4 kHzb25 kHz
fe25 kHzb50 kHz
40
40
36
dBC
dB
dB
SOS
Spurious Out-of-Band Signals
at the Channel Output
0 dBm0 300 Hzb3400 Hz Input
PCM Code Applied at DR
Measure Individual Image Signals at
VFRO
4600 Hz – 7600 Hz
7600 Hz – 8400 Hz
8400 Hz – 100 000 Hz
b32
b40
b32
dB
dB
dB
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet TP3064N.PDF ] | |
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