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PDF TP3057J Data sheet ( Hoja de datos )
| Número de pieza | TP3057J | |
| Descripción | Enhanced Serial Interface CODEC/Filter COMBO Family | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 1994
TP3054 TP3057
‘‘Enhanced’’ Serial Interface
CODEC Filter COMBO Family
General Description
The TP3054 TP3057 family consists of m-law and A-law
monolithic PCM CODEC filters utilizing the A D and D A
conversion architecture shown in Figure 1 and a serial PCM
interface The devices are fabricated using National’s ad-
vanced double-poly CMOS process (microCMOS)
The encode portion of each device consists of an input gain
adjust amplifier an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz Also included are auto-zero circuitry and a com-
panding coder which samples the filtered signal and en-
codes it in the companded m-law or A-law PCM format The
decode portion of each device consists of an expanding
decoder which reconstructs the analog signal from the
companded m-law or A-law code a low-pass filter which
corrects for the sin x x response of the decoder output and
rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads
The devices require two 1 536 MHz 1 544 MHz or 2 048
MHz transmit and receive master clocks which may be
asynchronous transmit and receive bit clocks which may
vary from 64 kHz to 2 048 MHz and transmit and receive
frame sync pulses The timing of the frame sync pulses and
PCM data is compatible with both industry standard formats
Features
Y Complete CODEC and filtering system (COMBO)
including
Transmit high-pass and low-pass filtering
Receive low-pass filter with sin x x correction
Active RC noise filters
m-law or A-law compatible COder and DECoder
Internal precision voltage reference
Serial I O interface
Internal auto-zero circuitry
Y m-law 16-pin TP3054
Y A-law 16-pin TP3057
Y Designed for D3 D4 and CCITT applications
Y g5V operation
Y Low operating power typically 50 mW
Y Power-down standby mode typically 3 mW
Y Automatic power-down
Y TTL or CMOS compatible digital interfaces
Y Maximizes line interface card circuit density
Y Dual-In-Line or surface mount packages
Y See also AN-370 ‘‘Techniques for Designing with
CODEC Filter COMBO Circuits’’
Connection Diagrams
Dual-In-Line Package
Plastic Chip Carriers
Top View
TL H 5510 – 1
Order Number TP3054J or TP3057J
See NS Package Number J16A
Order Number TP3054N or TP3057N
See NS Package Number N16A
Order Number TP3054WM or TP3057WM
See NS Package Number M16B
COMBO and TRI-STATE are registered trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL H 5510
Top View
TL H 5510 – 10
Order Number TP3057V
See NS Package Number V20A
RRD-B30M125 Printed in U S A
1 page  
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
VCC to GNDA
VBB to GNDA
Voltage at any Analog Input
or Output
7V
b7V
VCCa0 3V to VBBb0 3V
Voltage at any Digital Input or
Output
VCCa0 3V to GNDAb0 3V
Operating Temperature Range
b25 C to a 125 C
Storage Temperature Range
b65 C to a150 C
Lead Temperature (Soldering 10 seconds)
300 C
ESD (Human Body Model)
2000V
Latch-Up Immunity e 100 mA on any Pin
Electrical Characteristics Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC
e 5 0V g5% VBB e b5 0V g5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits
are assured by correlation with other production tests and or product design and characterization All signals referenced to
GNDA Typicals specified at VCC e 5 0V VBB e b5 0V TA e 25 C
Symbol
Parameter
Conditions
Min Typ Max Units
DIGITAL INTERFACE
VIL
VIH
VOL
VOH
IIL
IIH
IOZ
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Current in High Impedance
State (TRI-STATE)
DX ILe3 2 mA
SIGR ILe1 0 mA
TSX ILe3 2 mA Open Drain
DX IHeb3 2 mA
SIGR IHeb1 0 mA
GNDAsVINsVIL All Digital Inputs
VIHsVINsVCC
DX GNDAsVOsVCC
22
24
24
b10
b10
b10
06 V
V
04 V
04 V
04 V
V
V
10 mA
10 mA
10 mA
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
IIXA
RIXA
ROXA
RLXA
CLXA
VOXA
AVXA
FUXA
VOSXA
VCMXA
CMRRXA
Input Leakage Current
Input Resistance
Output Resistance
Load Resistance
Load Capacitance
Output Dynamic Range
Voltage Gain
Unity Gain Bandwidth
Offset Voltage
Common-Mode Voltage
Common-Mode Rejection Ratio
b2 5VsVsa2 5V VFXIa or VFXIb b200
200 nA
b2 5VsVsa2 5V VFXIa or VFXIb
10
MX
Closed Loop Unity Gain
13
X
GSX
GSX
GSX RLt10 kX
VFXIa to GSX
10 kX
50 pF
b2 8
28 V
5000
VV
12
MHz
b20
20 mV
CMRRXA l 60 dB
b2 5
25 V
DC Test
60 dB
PSRRXA Power Supply Rejection Ratio
DC Test
60 dB
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
RORF
Output Resistance
RLRF
Load Resistance
CLRF
Load Capacitance
VOSRO
Output DC Offset Voltage
POWER DISSIPATION (ALL DEVICES)
Pin VFRO
VFROe g2 5V
13
X
600 X
500 pF
b200
200 mV
ICC0
Power-Down Current
No Load (Note)
IBB0
Power-Down Current
No Load (Note)
ICC1
Power-Up Active Current
No Load
IBB1
Power-Up Active Current
No Load
Note ICC0 and IBB0 are measured after first achieving a power-up state
05 15
0 05 0 3
50 90
50 90
mA
mA
mA
mA
5
5 Page 
Transmission Characteristics (Continued) Unless otherwise noted limits printed in BOLD characters are
guaranteed for VCC e 5 0V g5% VBB e b5 0V g5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e
25 C All other limits are assured by correlation with other production tests and or product design and characterization GNDA
e 0V f e 1 02 kHz VIN e 0 dBm0 transmit input amplifier connected for unity gain non-inverting Typicals specified at VCC e
5 0V VBB e b5 0V TA e 25 C
Symbol
Parameter
Conditions
Min Typ Max Units
SOS
Spurious Out-of-Band Signals
at the Channel Output
Loop Around Measurement 0 dBm0
300 Hz to 3400 Hz Input PCM Code Applied
at DR
4600 Hz – 7600 Hz
7600 Hz – 8400 Hz
8400 Hz – 100 000 Hz
b30
dB
b30
b40
b30
dB
dB
dB
DISTORTION
STDX
STDR
Signal to Total Distortion
Transmit or Receive
Half-Channel
Sinusoidal Test Method (Note 3)
Level e3 0 dBm0
e0 dBm0 to b30 dBm0
eb40 dBm0 XMT
RCV
eb55 dBm0 XMT
RCV
33
36
29
30
14
15
dBC
dBC
dBC
dBC
dBC
dBC
SFDX
Single Frequency Distortion
Transmit
b46
dB
SFDR
Single Frequency Distortion
Receive
b46
dB
IMD Intermodulation Distortion
Loop Around Measurement
VFXa eb4 dBm0 to b21 dBm0 Two
Frequencies in the Range
300 Hz – 3400 Hz
b41
dB
CROSSTALK
CTX-R
CTR-X
Transmit to Receive Crosstalk
0 dBm0 Transmit Level
Receive to Transmit Crosstalk
0 dBm0 Receive Level
fe300 Hz – 3400 Hz
DReQuiet PCM Code
fe300 Hz – 3400 Hz VFXIeMultitone
(Note 2)
b90
b90
b75
b70
dB
dB
ENCODING FORMAT AT DX OUTPUT
TP3054
m-Law
TP3057
A-Law
(Includes Even Bit Inversion)
VIN (at GSX)e aFull-Scale
VIN (at GSX)e0V
10000000
11111111
01111111
1010101
1101010
0101010
VIN (at GSX)ebFull-Scale
00000000
0010101
Note 1 Measured by extrapolation from the distortion test result at b50 dBm0
Note 2 PPSRX NPSRX and CTR-X are measured with a b50 dBm0 activation signal applied to VFXIa
Note 3 Devices are measured using C message weighted filter for m-Law and psophometric weighted filter for A-Law
0
1
1
0
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TP3057J.PDF ] | |
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