|
|
PDF TMS416409A Data sheet ( Hoja de datos )
| Número de pieza | TMS416409A | |
| Descripción | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TMS416409A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
This data sheet is applicable to all
TMS41x409As and TMS42x409As symbolized
by Revision “B”, Revision “E”, and subsequent
revisions as described in the device
symbolization section.
D Organization . . . 4 194304 × 4
D Single Power Supply (5 V or 3.3 V)
D Performance Ranges:
’41x409A-50
’41x409A-60
ACCESS ACCESS ACCESS
TIME TIME TIME
tRAC
MAX
tCAC
MAX
tAA
MAX
50 ns 13 ns 25 ns
60 ns 15 ns 30 ns
EDO
CYCLE
tHPC
MIN
20 ns
25 ns
’41x409A-70
’42x409A-50
70 ns
50 ns
18 ns
13 ns
35 ns
25 ns
30 ns
20 ns
’42x409A-60
60 ns 15 ns 30 ns
25 ns
’42x409A-70
70 ns 18 ns 35 ns
30 ns
D Extended-Data-Out (EDO) Operation
D CAS-Before-RAS ( CBR) Refresh
D Low Power Dissipation
D 3-State Unlatched Output
D High-Reliability Plastic 24 / 26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DJ Suffix) and
24/26-Lead 300-Mil-Wide Surface-Mount
Thin Small-Outline Package (TSOP)
(DGA Suffix)
D Operating Free-Air Temperature Range
0°C to 70°C
description
The TMS41x409A and TMS42x409A series are
16 777 216-bit dynamic random-access memory
(DRAM) devices organized as 4 194 304 words of
four bits each.
These devices feature maximum RAS access
times of 50, 60, and 70 ns. All address and data-in
lines are latched on chip to simplify system
design. Data out is unlatched to allow greater
system flexibility.
DJ/DGA PACKAGES
( TOP VIEW )
VCC
DQ1
DQ2
W
RAS
A11†
1
2
3
4
5
6
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
21 A9
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
PIN NOMENCLATURE
A0 – A11†
DQ1 – DQ4
CAS
NC
OE
RAS
VCC
VSS
W
Address Inputs
Data In / Data Out
Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
5-V or 3.3-V Supply‡
Ground
Write Enable
† A11 is NC for TMS417409A and TMS427409A.
‡ See Available Options Table
DEVICE
TMS416409A
TMS417409A
TMS426409A
TMS427409A
AVAILABLE OPTIONS
POWER
SUPPLY
SELF
REFRESH,
BATTERY
BACKUP
5V –
5V –
3.3 V
–
3.3 V
–
REFRESH
CYCLES
4 096 in 64 ms
2 048 in 32 ms
4 096 in 64 ms
2 048 in 32 ms
The TMS416409A and TMS417409A are offered in a 24 / 26-lead plastic surface-mount SOJ package
(DJ suffix). The TMS426409A and TMS427409A are offered in a 24/26-lead plastic surface-mount SOJ
package (DJ suffix) and a 24 / 26-lead plastic surface-mount TSOP (DGA suffix). These packages are designed
for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
•POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1
1 page  
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
operation
extended data out
Extended data out (EDO) allows data output rates of up to 50 MHz for 50-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold and for address
multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the
maximum RAS low time.
Extended data out does not place the data in / data out pins (DQ pins) into the high-impedance state with the
rising edge of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM
decodes the next address. OE and W can control the output impedance. Descriptions of OE and W further
explain EDO operation benefit.
address: A0 – A11 ( TMS416409A and TMS426409A) and A0 – A10 (TMS417409A and TMS427409A)
Twenty-two address bits are required to decode each of the 4 194 304 storage cell locations. For the
TMS416409A and TMS426409A,12 row-address bits are set up on A0 through A11 and latched onto the chip
by the row-address strobe (RAS). Ten column-address bits are set up on A0 through A9. For the TMS417409A
and TMS427409A, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS.
Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling
edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the
column-address buffers.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two
methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE
from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS
falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a
minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further
transitions on OE until CAS falls again (see Figure 8).
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high
(see Figure 9).
data in / data out (DQ1 – DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the later falling
edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge.
The DQs drive valid data after all access times are met and remain valid except in cases described in the W
and OE sections.
•POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
5
5 Page 
TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS426409A
PARAMETER
TEST CONDITIONS†
’426409A - 50
MIN MAX
’426409A -60
MIN MAX
’426409A - 70
MIN MAX
VOH
High-level
output
voltage
IOH = – 2 mA
IOH = – 100 µA
LVTTL
LVCMOS
2.4
VCC – 0.2
2.4
VCC – 0.2
2.4
VCC – 0.2
VOL
Low-level
output
voltage
IOL = 2 mA
IOL = 100 µA
LVTTL
LVCMOS
0.4 0.4 0.4
0.2 0.2 0.2
II
Input current
(leakage)
VCC = 3.6 V, VI = 0 V to 3.9 V,
All others = 0 V to VCC
IO
Output
current
(leakage)
VCC = 3.6 V,
CAS high
VO = 0 V to VCC,
± 10 ± 10 ± 10
± 10 ± 10 ± 10
ICC1‡§
Average
read- or
write- cycle
current
VCC = 3.6 V,
Minimum cycle
90 70 60
ICC2
Average
standby
current
VIH = 2 V (LVTTL)
After one memory cycle, RAS and CAS
high
VIH = VCC – 0.2 V (LVCMOS),
After one memory cycle, RAS and CAS
high
222
111
ICC3‡§
Average
refresh
current
(RAS-only
refresh
or CBR)
VCC = 3.6 V,
RAS cycling,
Minimum cycle,
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
90 70 60
ICC4‡¶
Average
EDO current
VCC = 3.6 V,
RAS low,
tHPC = MIN,
CAS cycling
100
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
90
80
UNIT
V
V
µA
µA
mA
mA
mA
mA
mA
•POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TMS416409A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TMS416409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES | National Semiconductor |
| TMS416409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES | National Semiconductor |
| TMS416409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES | National Semiconductor |
| TMS416409A | 4194304 By 4-Bit Extended Data Out Dynamic Random-Access Memories (Rev. B) |  Texas Instruments |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |